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authorCaesar Wang <wxt@rock-chips.com>2017-06-19 14:02:52 +0800
committerCaesar Wang <wxt@rock-chips.com>2017-06-30 08:46:20 +0800
commitc3710ee7a2360c946a3e06e471a6205279729145 (patch)
tree610c27642ee9ac9f31350a395cd7505cdb34ce96 /plat/rockchip
parentaa5b843fe8f2d8cea80fd1c06e7fc6b7c18f265c (diff)
rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume
This patch fixes the two things as follows: 1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash". 2) fixes the warnings log. We always hit the warnings thing during the suspend, as below log: .. [ 51.022334] CPU5: shutdown [ 51.025069] psci: CPU5 killed. INFO: sdram_params->ddr_freq = 928000000 WARNING: rk3399_flash_l2_b:reg 28830380,wait When the L2 completes the clean and invalidate sequence, it asserts the L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then the L2 deasserts L2FLUSHDONE. Then, a loop without a delay isn't really great to measure time. We should probably add a udelay(10) or so in there and then maybe replace the WARN() after the loop. In the actual tests, the L2 cache will take ~4ms by default for big cluster. In the real world that give 10ms for the enough margin, like the ddr/cpu/cci frequency and other factors that will affect it. Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'plat/rockchip')
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index f6c47f43..37977e14 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -362,19 +362,23 @@ static void pmu_power_domains_resume(void)
clk_gate_con_restore();
}
-void rk3399_flash_l2_b(void)
+void rk3399_flush_l2_b(void)
{
uint32_t wait_cnt = 0;
mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
dsb();
+ /*
+ * The Big cluster flush L2 cache took ~4ms by default, give 10ms for
+ * the enough margin.
+ */
while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
BIT(L2_FLUSHDONE_CLUSTER_B))) {
wait_cnt++;
- if (wait_cnt >= MAX_WAIT_COUNT)
- WARN("%s:reg %x,wait\n", __func__,
- mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
+ udelay(10);
+ if (wait_cnt == 10000 / 10)
+ WARN("L2 cache flush on suspend took longer than 10ms\n");
}
mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
@@ -391,7 +395,7 @@ static void pmu_scu_b_pwrdn(void)
return;
}
- rk3399_flash_l2_b();
+ rk3399_flush_l2_b();
mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));