diff options
| author | Derek Basehore <dbasehore@chromium.org> | 2018-01-23 15:44:31 -0800 |
|---|---|---|
| committer | Derek Basehore <dbasehore@chromium.org> | 2018-01-23 17:42:47 -0800 |
| commit | aa9ee82dc1e0790886a0cee6e5c9681f0d324aac (patch) | |
| tree | 69af1db16fb7c248f12e17f123ceb75f2b462379 /plat/rockchip | |
| parent | c1edcd935deabaa1b7d28c5c56e4674c05b635f2 (diff) | |
rockchip/rk3399: Change PD_CTR_LOOP to 10000
This brings ATF into line with the kernel on the timeout for power
domains turning on. We could actually timeout (when we shouldn't) on
resume when turning power domains on. The guaranteed maximum delay is
now 10ms.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h index 5c0ab4d7..0265dde4 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.h +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -53,7 +53,7 @@ enum pmu_core_pwrst_shift { #define TSADC_INT_PIN 38 #define CORES_PM_DISABLE 0x0 -#define PD_CTR_LOOP 500 +#define PD_CTR_LOOP 10000 #define CHK_CPU_LOOP 500 #define MAX_WAIT_COUNT 1000 |