diff options
author | tony.xie <tony.xie@rock-chips.com> | 2017-03-01 11:05:17 +0800 |
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committer | tony.xie <tony.xie@rock-chips.com> | 2017-03-01 11:09:16 +0800 |
commit | f32ab4445a669cb44d51c97f388bb363ad22b824 (patch) | |
tree | 96e339d7766c8e1752dca14235b3945c2b171e75 /plat/rockchip/rk3399 | |
parent | bcc2bf097703c07aabe543681ee2676981831f76 (diff) |
rockchip: plat_pm.c: Change callbacks implement for our SOCs.
Remove struct rockchip_pm_ops_cb and instead of using weak functions
implement; in this way we want the codes look clear and simple;
Change-Id: Ib9e8a5e932fdfc2b3e6a1ec502c40dfe720ac400
Signed-off-by: tony.xie <tony.xie@rock-chips.com>
Diffstat (limited to 'plat/rockchip/rk3399')
-rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/pmu.c | 64 |
1 files changed, 24 insertions, 40 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c index 05ca7fdd..5bb29b3b 100644 --- a/plat/rockchip/rk3399/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -623,7 +623,7 @@ static void nonboot_cpus_off(void) } } -static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) +int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) { uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); @@ -635,19 +635,20 @@ static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) cpus_power_domain_on(cpu_id); - return 0; + return PSCI_E_SUCCESS; } -static int cores_pwr_domain_off(void) +int rockchip_soc_cores_pwr_dm_off(void) { uint32_t cpu_id = plat_my_core_pos(); cpus_power_domain_off(cpu_id, core_pwr_wfi); - return 0; + return PSCI_E_SUCCESS; } -static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state) +int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, + plat_local_state_t lvl_state) { switch (lvl) { case MPIDR_AFFLVL1: @@ -657,10 +658,10 @@ static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state) break; } - return 0; + return PSCI_E_SUCCESS; } -static int cores_pwr_domain_suspend(void) +int rockchip_soc_cores_pwr_dm_suspend(void) { uint32_t cpu_id = plat_my_core_pos(); @@ -672,10 +673,10 @@ static int cores_pwr_domain_suspend(void) cpus_power_domain_off(cpu_id, core_pwr_wfi_int); - return 0; + return PSCI_E_SUCCESS; } -static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state) +int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state) { switch (lvl) { case MPIDR_AFFLVL1: @@ -685,20 +686,20 @@ static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state) break; } - return 0; + return PSCI_E_SUCCESS; } -static int cores_pwr_domain_on_finish(void) +int rockchip_soc_cores_pwr_dm_on_finish(void) { uint32_t cpu_id = plat_my_core_pos(); mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); - return 0; + return PSCI_E_SUCCESS; } -static int hlvl_pwr_domain_on_finish(uint32_t lvl, - plat_local_state_t lvl_state) +int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, + plat_local_state_t lvl_state) { switch (lvl) { case MPIDR_AFFLVL1: @@ -708,20 +709,20 @@ static int hlvl_pwr_domain_on_finish(uint32_t lvl, break; } - return 0; + return PSCI_E_SUCCESS; } -static int cores_pwr_domain_resume(void) +int rockchip_soc_cores_pwr_dm_resume(void) { uint32_t cpu_id = plat_my_core_pos(); /* Disable core_pm */ mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); - return 0; + return PSCI_E_SUCCESS; } -static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state) +int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state) { switch (lvl) { case MPIDR_AFFLVL1: @@ -730,7 +731,7 @@ static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state) break; } - return 0; + return PSCI_E_SUCCESS; } /** @@ -1097,7 +1098,7 @@ static void m0_reset(void) BITS_WITH_WMASK(0x2f, 0x2f, 0)); } -static int sys_pwr_domain_suspend(void) +int rockchip_soc_sys_pwr_dm_suspend(void) { uint32_t wait_cnt = 0; uint32_t status = 0; @@ -1160,7 +1161,7 @@ static int sys_pwr_domain_suspend(void) return 0; } -static int sys_pwr_domain_resume(void) +int rockchip_soc_sys_pwr_dm_resume(void) { uint32_t wait_cnt = 0; uint32_t status = 0; @@ -1247,7 +1248,7 @@ static int sys_pwr_domain_resume(void) return 0; } -void __dead2 soc_soft_reset(void) +void __dead2 rockchip_soc_soft_reset(void) { struct gpio_info *rst_gpio; @@ -1264,7 +1265,7 @@ void __dead2 soc_soft_reset(void) ; } -void __dead2 soc_system_off(void) +void __dead2 rockchip_soc_system_off(void) { struct gpio_info *poweroff_gpio; @@ -1289,28 +1290,11 @@ void __dead2 soc_system_off(void) ; } -static struct rockchip_pm_ops_cb pm_ops = { - .cores_pwr_dm_on = cores_pwr_domain_on, - .cores_pwr_dm_off = cores_pwr_domain_off, - .cores_pwr_dm_on_finish = cores_pwr_domain_on_finish, - .cores_pwr_dm_suspend = cores_pwr_domain_suspend, - .cores_pwr_dm_resume = cores_pwr_domain_resume, - .hlvl_pwr_dm_suspend = hlvl_pwr_domain_suspend, - .hlvl_pwr_dm_resume = hlvl_pwr_domain_resume, - .hlvl_pwr_dm_off = hlvl_pwr_domain_off, - .hlvl_pwr_dm_on_finish = hlvl_pwr_domain_on_finish, - .sys_pwr_dm_suspend = sys_pwr_domain_suspend, - .sys_pwr_dm_resume = sys_pwr_domain_resume, - .sys_gbl_soft_reset = soc_soft_reset, - .system_off = soc_system_off, -}; - void plat_rockchip_pmu_init(void) { uint32_t cpu; rockchip_pd_lock_init(); - plat_setup_rockchip_pm_ops(&pm_ops); /* register requires 32bits mode, switch it to 32 bits */ cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; |