diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-12-26 15:57:08 +0100 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2019-01-08 14:08:44 +0100 |
| commit | bc5fabd813e65967e0929d402fc437829c222564 (patch) | |
| tree | 3d3010a39d1dba0219ac37c74224f87cb05919b9 /plat/renesas | |
| parent | fc181c3b2c144ba8e6c80bd45e572633a833125f (diff) | |
rcar_gen3: plat: Fix BL2 size check
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to
correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the
hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable
BL2 area.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'plat/renesas')
| -rw-r--r-- | plat/renesas/rcar/bl2_plat_setup.c | 2 | ||||
| -rw-r--r-- | plat/renesas/rcar/include/platform_def.h | 8 | ||||
| -rw-r--r-- | plat/renesas/rcar/include/rcar_def.h | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index b0ce0698..115190dc 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -899,7 +899,7 @@ void bl2_el3_plat_arch_setup(void) #if RCAR_BL2_DCACHE == 1 NOTICE("BL2: D-Cache enable\n"); rcar_configure_mmu_el3(BL2_BASE, - RCAR_SYSRAM_LIMIT - BL2_BASE, + BL2_END - BL2_BASE, BL2_RO_BASE, BL2_RO_LIMIT #if USE_COHERENT_MEM , BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT diff --git a/plat/renesas/rcar/include/platform_def.h b/plat/renesas/rcar/include/platform_def.h index 57399a24..934b2dcd 100644 --- a/plat/renesas/rcar/include/platform_def.h +++ b/plat/renesas/rcar/include/platform_def.h @@ -104,16 +104,16 @@ * size plus a little space for growth. */ #define RCAR_SYSRAM_BASE U(0xE6300000) #if RCAR_LSI == RCAR_E3 -#define RCAR_SYSRAM_LIMIT U(0xE6320000) +#define BL2_LIMIT U(0xE6320000) #else -#define RCAR_SYSRAM_LIMIT U(0xE6360000) +#define BL2_LIMIT U(0xE6360000) #endif #define BL2_BASE U(0xE6304000) #if RCAR_LSI == RCAR_E3 -#define BL2_LIMIT U(0xE6318000) +#define BL2_IMAGE_LIMIT U(0xE6318000) #else -#define BL2_LIMIT U(0xE632E800) +#define BL2_IMAGE_LIMIT U(0xE632E800) #endif #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE) diff --git a/plat/renesas/rcar/include/rcar_def.h b/plat/renesas/rcar/include/rcar_def.h index 242e007b..3dbd3f58 100644 --- a/plat/renesas/rcar/include/rcar_def.h +++ b/plat/renesas/rcar/include/rcar_def.h @@ -24,7 +24,7 @@ #define DEVICE_RCAR_SIZE U(0x00300000) #define DEVICE_RCAR_BASE2 U(0xE6360000) #define DEVICE_RCAR_SIZE2 U(0x19CA0000) -#define DEVICE_SRAM_BASE U(0xE6310000) +#define DEVICE_SRAM_BASE U(0xE6300000) #define DEVICE_SRAM_SIZE U(0x00002000) #define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) #define DEVICE_SRAM_STACK_SIZE U(0x00001000) |