diff options
| author | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-10-02 20:43:09 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2018-12-06 01:59:10 +0100 |
| commit | 851851519d2672e02699f6ade92739adda0bb6b7 (patch) | |
| tree | a88a979aba39c51302ce7ec37bc35eacfc0c11f9 /plat/renesas | |
| parent | 10b7a4aeca441a6d3ca1f411bf479e119a249229 (diff) | |
plat: rcar: Use array in the DRAM size reporting
Use array of start-size tuples for the DRAM banks and call single
function which iterates over this array to report the DRAM info.
This is in preparation for expanding this to generate FDT for the
next stage.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'plat/renesas')
| -rw-r--r-- | plat/renesas/rcar/bl2_plat_setup.c | 57 |
1 files changed, 41 insertions, 16 deletions
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c index b2865394..75b9b900 100644 --- a/plat/renesas/rcar/bl2_plat_setup.c +++ b/plat/renesas/rcar/bl2_plat_setup.c @@ -300,55 +300,80 @@ meminfo_t *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } +static void bl2_advertise_dram_entries(uint64_t dram_config[8]) +{ + uint64_t start, size; + int chan; + + for (chan = 0; chan < 4; chan++) { + start = dram_config[2 * chan]; + size = dram_config[2 * chan + 1]; + if (!size) + continue; + + NOTICE("BL2: CH%d: %llx - %llx, %lld GiB\n", + chan, start, start + size - 1, size >> 30); + } +} + static void bl2_advertise_dram_size(uint32_t product) { + uint64_t dram_config[8] = { + [0] = 0x400000000ULL, + [2] = 0x500000000ULL, + [4] = 0x600000000ULL, + [6] = 0x700000000ULL, + }; + switch (product) { case RCAR_PRODUCT_H3: #if (RCAR_DRAM_LPDDR4_MEMCONF == 0) /* 4GB(1GBx4) */ - NOTICE("BL2: CH0: 0x400000000 - 0x43fffffff, 1 GiB\n"); - NOTICE("BL2: CH1: 0x500000000 - 0x53fffffff, 1 GiB\n"); - NOTICE("BL2: CH2: 0x600000000 - 0x63fffffff, 1 GiB\n"); - NOTICE("BL2: CH3: 0x700000000 - 0x73fffffff, 1 GiB\n"); + dram_config[1] = 0x40000000ULL; + dram_config[3] = 0x40000000ULL; + dram_config[5] = 0x40000000ULL; + dram_config[7] = 0x40000000ULL; #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && \ (RCAR_DRAM_CHANNEL == 5) && \ (RCAR_DRAM_SPLIT == 2) /* 4GB(2GBx2 2ch split) */ - NOTICE("BL2: CH0: 0x400000000 - 0x47fffffff, 2 GiB\n"); - NOTICE("BL2: CH1: 0x500000000 - 0x57fffffff, 2 GiB\n"); + dram_config[1] = 0x80000000ULL; + dram_config[3] = 0x80000000ULL; #elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15) /* 8GB(2GBx4: default) */ - NOTICE("BL2: CH0: 0x400000000 - 0x47fffffff, 2 GiB\n"); - NOTICE("BL2: CH1: 0x500000000 - 0x57fffffff, 2 GiB\n"); - NOTICE("BL2: CH2: 0x600000000 - 0x67fffffff, 2 GiB\n"); - NOTICE("BL2: CH3: 0x700000000 - 0x77fffffff, 2 GiB\n"); + dram_config[1] = 0x80000000ULL; + dram_config[3] = 0x80000000ULL; + dram_config[5] = 0x80000000ULL; + dram_config[7] = 0x80000000ULL; #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ break; case RCAR_PRODUCT_M3: /* 4GB(2GBx2 2ch split) */ - NOTICE("BL2: CH0: 0x400000000 - 0x480000000, 2 GiB\n"); - NOTICE("BL2: CH1: 0x600000000 - 0x680000000, 2 GiB\n"); + dram_config[1] = 0x80000000ULL; + dram_config[5] = 0x80000000ULL; break; case RCAR_PRODUCT_M3N: /* 2GB(1GBx2) */ - NOTICE("BL2: 0x400000000 - 0x480000000, 2 GiB\n"); + dram_config[1] = 0x80000000ULL; break; case RCAR_PRODUCT_E3: #if (RCAR_DRAM_DDR3L_MEMCONF == 0) /* 1GB(512MBx2) */ - NOTICE("BL2: 0x400000000 - 0x43fffffff, 1 GiB\n"); + dram_config[1] = 0x40000000ULL; #elif (RCAR_DRAM_DDR3L_MEMCONF == 1) /* 2GB(512MBx4) */ - NOTICE("BL2: 0x400000000 - 0x47fffffff, 2 GiB\n"); + dram_config[1] = 0x80000000ULL; #elif (RCAR_DRAM_DDR3L_MEMCONF == 2) /* 4GB(1GBx4) */ - NOTICE("BL2: 0x400000000 - 0x4ffffffff, 4 GiB\n"); + dram_config[1] = 0x100000000ULL; #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ break; } + + bl2_advertise_dram_entries(dram_config); } void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, |