diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-02-21 14:40:44 +0000 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-05-02 16:11:12 +0100 |
| commit | f4c8aa905414fb021c08370306bd516f678a58bd (patch) | |
| tree | 7f727d80afb45c86cf12203e66d49bf23d5bd0b6 /plat/qemu | |
| parent | 7fa3214e18ad640208eaf6c8d6111ec53f3894aa (diff) | |
Add macro to check whether the CPU implements an EL
Replace all instances of checks with the new macro.
Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'plat/qemu')
| -rw-r--r-- | plat/qemu/qemu_bl2_setup.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 738d671a..6c599744 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -226,15 +226,11 @@ static uint32_t qemu_get_spsr_for_bl32_entry(void) ******************************************************************************/ static uint32_t qemu_get_spsr_for_bl33_entry(void) { - unsigned long el_status; unsigned int mode; uint32_t spsr; /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; + mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; /* * TODO: Consider the possibility of specifying the SPSR in |