diff options
| author | Steven Kao <skao@nvidia.com> | 2018-02-09 20:50:02 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2019-01-31 08:47:51 -0800 |
| commit | 1d11f73e581bfbe9945a298ab1c4fd5ff261f6e7 (patch) | |
| tree | 9adf056082ad58964b61045367deab4151051998 /plat/nvidia | |
| parent | 26cf08494b3db526c4b887d27c797da49efb7505 (diff) | |
Tegra: platform dependent address space sizes
This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.
Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6
Signed-off-by: Steven Kao <skao@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/include/platform_def.h | 8 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t132/tegra_def.h | 8 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_def.h | 8 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t210/tegra_def.h | 6 |
4 files changed, 21 insertions, 9 deletions
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h index 0a0126b1..334ad129 100644 --- a/plat/nvidia/tegra/include/platform_def.h +++ b/plat/nvidia/tegra/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,12 +54,6 @@ #define BL32_LIMIT TZDRAM_END /******************************************************************************* - * Platform specific page table and MMU setup constants - ******************************************************************************/ -#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) -#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) - -/******************************************************************************* * Some data must be aligned on the biggest cache line size in the platform. * This is known only to the platform as it might have a combination of * integrated and external caches. diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h index 2fe321b2..dfed2aa6 100644 --- a/plat/nvidia/tegra/include/t132/tegra_def.h +++ b/plat/nvidia/tegra/include/t132/tegra_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,6 +25,12 @@ #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) /******************************************************************************* + * Chip specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) + +/******************************************************************************* * GIC memory map ******************************************************************************/ #define TEGRA_GICD_BASE U(0x50041000) diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 2603ccb2..da050a89 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -58,6 +58,12 @@ #define PLAT_MAX_OFF_STATE U(8) /******************************************************************************* + * Chip specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) + +/******************************************************************************* * Secure IRQ definitions ******************************************************************************/ #define TEGRA186_TOP_WDT_IRQ U(49) diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h index 6a820f00..02a49b8f 100644 --- a/plat/nvidia/tegra/include/t210/tegra_def.h +++ b/plat/nvidia/tegra/include/t210/tegra_def.h @@ -33,6 +33,12 @@ #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) /******************************************************************************* + * Chip specific page table and MMU setup constants + ******************************************************************************/ +#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35) +#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35) + +/******************************************************************************* * iRAM memory constants ******************************************************************************/ #define TEGRA_IRAM_BASE 0x40000000 |