diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-05 14:54:46 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-14 15:00:13 -0700 |
| commit | fb7d32e5881ef2445e8fe2305005f5590d4a7cfa (patch) | |
| tree | 24c77f58069dddfc1e8c530d06f9bf94bc77f613 /plat/nvidia | |
| parent | 6311f63de02ee04d93016242977ade4727089de8 (diff) | |
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/common/aarch64/tegra_helpers.S | 34 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_setup.c | 4 |
2 files changed, 19 insertions, 19 deletions
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index 1a4236fd..22389f27 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -68,18 +68,18 @@ * Enable processor retention * --------------------------- */ - mrs x0, L2ECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT - bic x0, x0, #L2ECTLR_RET_CTRL_MASK + mrs x0, CORTEX_A57_L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK orr x0, x0, x1 - msr L2ECTLR_EL1, x0 + msr CORTEX_A57_L2ECTLR_EL1, x0 isb - mrs x0, CPUECTLR_EL1 - mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT - bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK + mrs x0, CORTEX_A57_ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 + bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK orr x0, x0, x1 - msr CPUECTLR_EL1, x0 + msr CORTEX_A57_ECTLR_EL1, x0 isb /* ------------------------------------------------------- @@ -98,11 +98,11 @@ adr x0, tegra_enable_l2_ecc_parity_prot ldr x0, [x0] cbz x0, 1f - mrs x0, L2CTLR_EL1 - and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT + mrs x0, CORTEX_A57_L2CTLR_EL1 + and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT cbnz x1, 1f - orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT - msr L2CTLR_EL1, x0 + orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT + msr CORTEX_A57_L2CTLR_EL1, x0 isb /* -------------------------------- @@ -317,18 +317,18 @@ func tegra_secure_entrypoint * entries from the branch predictor array. * ------------------------------------------------------- */ - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 orr x0, x0, #1 - msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */ dsb sy isb ic iallu /* actual invalidate */ dsb sy isb - mrs x0, CPUACTLR_EL1 + mrs x0, CORTEX_A57_ACTLR_EL1 bic x0, x0, #1 - msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ dsb sy isb @@ -352,7 +352,7 @@ func tegra_secure_entrypoint msr oslar_el1, x0 /* os lock stays 0 across warm reset */ mov x3, #3 movz x4, #0x8000, lsl #48 - msr CPUACTLR_EL1, x4 /* turn off RCG */ + msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */ isb msr rmr_el3, x3 /* request warm reset */ isb diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index 151b7570..ba245790 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -22,7 +22,7 @@ #include <tegra_private.h> #include <xlat_tables.h> -DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1) extern uint64_t tegra_enable_l2_ecc_parity_prot; /******************************************************************************* @@ -172,7 +172,7 @@ void plat_early_platform_setup(void) if (val >= TEGRA186_VER_A02P) { val = read_l2ctlr_el1(); - val |= L2_ECC_PARITY_PROTECTION_BIT; + val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; write_l2ctlr_el1(val); /* |