diff options
| author | Harvey Hsieh <hhsieh@nvidia.com> | 2016-11-15 22:04:51 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-04-07 09:32:28 -0700 |
| commit | c4dae9fc69477474ed227dd93f9ba0ffd09245b4 (patch) | |
| tree | ed24d90cd4623b6bb362010c94faef62516b87db /plat/nvidia | |
| parent | 5dc574b4cd2ab7f6c4eb9ccc64592df912e02d45 (diff) | |
Tegra: memctrl_v2: remove non-secure access to TZSRAM memory
This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.
Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 9 | ||||
| -rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_def.h | 2 |
2 files changed, 1 insertions, 10 deletions
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index 18f33682..5986416e 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -679,13 +679,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) tegra_mc_write_32(index, 0); /* - * Allow CPU read/write access to the aperture - */ - tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1, - TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT | - TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT); - - /* * Set the TZRAM base. TZRAM base must be 4k aligned, at least. */ assert(!(phys_base & 0xFFF)); diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index f919ac37..8a1dd3f2 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -182,8 +182,6 @@ #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 -#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) -#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 |