diff options
author | Varun Wadekar <vwadekar@nvidia.com> | 2017-04-18 09:55:54 -0700 |
---|---|---|
committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-14 17:00:53 -0700 |
commit | 368d54502cc9b92d3c3d374b2de7ae09286c86f7 (patch) | |
tree | 54a3f7c912fb696052a1472a1069c78bf6d60e3a /plat/nvidia | |
parent | 70cb692e234155b7b831ee2414a0818b26c0b7df (diff) |
Tegra: memctrl_v2: fix software logic to check "flush complete"
This patch fixes the logic to check if the command written to the
MC_CLIENT_HOTRESET_CTRLx registers, was accepted by the hardware module.
Change-Id: If94fff9424555cb4688042eda17b4b20f4eb399a
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia')
-rw-r--r-- | plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c index e0e67d5c..76e21f6d 100644 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c @@ -254,32 +254,12 @@ static void tegra_memctrl_reconfig_mss_clients(void) wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0); - /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); - } while ((val & wdata_0) != wdata_0); - - /* Wait one more time due to SW WAR for known legacy issue */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0); - } while ((val & wdata_0) != wdata_0); - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1); assert(val == wdata_1); wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL; tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1); - /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); - } while ((val & wdata_1) != wdata_1); - - /* Wait one more time due to SW WAR for known legacy issue */ - do { - val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1); - } while ((val & wdata_1) != wdata_1); - #endif } |