diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-09-14 15:57:44 +0100 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2017-09-21 12:03:53 +0100 |
| commit | e47ac1fd634a3934d7d3ac446190b2f4bd8a640f (patch) | |
| tree | 4291bffc8b34a4d395bbee467ee5fcaff2bcdbeb /plat/nvidia | |
| parent | df312c5a2b152953f755df9d979cff20afb7ef4b (diff) | |
Fix type of `unsigned long` constants
The type `unsigned long` is 32 bit wide in AArch32, but 64 bit wide in
AArch64. This is inconsistent and that's why we avoid using it as per
the Coding Guidelines. This patch changes all `UL` occurrences to `U`
or `ULL` depending on the context so that the size of the constant is
clear.
This problem affected the macro `BIT(nr)`. As long as this macro is used
to fill fields of registers, that's not a problem, since all registers
are 32 bit wide in AArch32 and 64 bit wide in AArch64. However, if the
macro is used to fill the fields of a 64-bit integer, it won't be able
to set the upper 32 bits in AArch32.
By changing the type of this macro to `unsigned long long` the behaviour
is always the same regardless of the architecture, as this type is
64-bit wide in both cases.
Some Tegra platform files have been modified by this patch.
Change-Id: I918264c03e7d691a931f0d1018df25a2796cc221
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'plat/nvidia')
| -rw-r--r-- | plat/nvidia/tegra/common/tegra_gic.c | 6 | ||||
| -rw-r--r-- | plat/nvidia/tegra/soc/t186/drivers/mce/ari.c | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/plat/nvidia/tegra/common/tegra_gic.c b/plat/nvidia/tegra/common/tegra_gic.c index e480e772..3ace554d 100644 --- a/plat/nvidia/tegra/common/tegra_gic.c +++ b/plat/nvidia/tegra/common/tegra_gic.c @@ -237,10 +237,10 @@ static uint32_t tegra_gic_get_pending_interrupt_id(void) id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; - if (id < 1022UL) { + if (id < 1022U) { ret = id; - } else if (id == 1023UL) { - ret = 0xFFFFFFFFUL; /* INTR_ID_UNAVAILABLE */ + } else if (id == 1023U) { + ret = 0xFFFFFFFFU; /* INTR_ID_UNAVAILABLE */ } else { /* * Find out which non-secure interrupt it is under the assumption that diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c index d34f7e28..7eb6c6c8 100644 --- a/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c +++ b/plat/nvidia/tegra/soc/t186/drivers/mce/ari.c @@ -435,7 +435,7 @@ uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data) ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA, (uint32_t)mca_arg_data, - (uint32_t)(mca_arg_data >> 32UL)); + (uint32_t)(mca_arg_data >> 32U)); if (ret == 0) { resp_lo = ari_get_response_low(ari_base); resp_hi = ari_get_response_high(ari_base); @@ -450,7 +450,7 @@ uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data) if (data != NULL) { resp_lo = ari_get_request_low(ari_base); resp_hi = ari_get_request_high(ari_base); - *data = ((uint64_t)resp_hi << 32UL) | + *data = ((uint64_t)resp_hi << 32U) | (uint64_t)resp_lo; } } @@ -513,7 +513,7 @@ int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req, * to the uncore perfmon registers */ val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ? - (uint32_t)*data : 0UL; + (uint32_t)*data : 0U; ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val, (uint32_t)req); |