diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2016-12-21 14:50:18 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-05-01 15:33:31 -0700 |
| commit | 9d42d23a2cb1394d0c9cf396dda7a362908da020 (patch) | |
| tree | b2570e5a40b963550ceecca9b697505586acbae8 /plat/nvidia/tegra/include | |
| parent | e9cb01d96e2615d65885f22731b1ebec0a53fd85 (diff) | |
Tegra: memctrl_v2: zero out NS Video memory carveout region
The video memory carveout has to be re-sized depending on the Video
content. This requires the NS world to send us new base/size values.
Before setting up the new region, we must zero out the previous memory
region, so that the video frames are not leaked to the outside world.
This patch adds the logic to zero out the previous memory carveout
region.
Change-Id: I471167ef7747154440df5c1a5e015fbeb69d9043
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/include')
| -rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_def.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h index 6693cb3a..8d7ab6ea 100644 --- a/plat/nvidia/tegra/include/t186/tegra_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_def.h @@ -157,6 +157,16 @@ #define TEGRA_MC_STREAMID_BASE 0x02C00000 #define TEGRA_MC_BASE 0x02C10000 +/* General Security Carveout register macros */ +#define MC_GSC_CONFIG_REGS_SIZE 0x40UL +#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1UL << 1) +#define MC_GSC_ENABLE_TZ_LOCK_BIT (1UL << 0) +#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27UL +#define MC_GSC_BASE_LO_SHIFT 12UL +#define MC_GSC_BASE_LO_MASK 0xFFFFFUL +#define MC_GSC_BASE_HI_SHIFT 0UL +#define MC_GSC_BASE_HI_MASK 3UL + /* TZDRAM carveout configuration registers */ #define MC_SECURITY_CFG0_0 0x70 #define MC_SECURITY_CFG1_0 0x74 @@ -165,34 +175,24 @@ /* Video Memory carveout configuration registers */ #define MC_VIDEO_PROTECT_BASE_HI 0x978 #define MC_VIDEO_PROTECT_BASE_LO 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_SIZE_MB 0x64C + +/* + * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the + * non-overlapping Video memory region + */ +#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 +#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 +#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 +#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC +#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ +#define MC_TZRAM_CARVEOUT_CFG 0x2190 #define MC_TZRAM_BASE_LO 0x2194 -#define TZRAM_BASE_LO_SHIFT 12 -#define TZRAM_BASE_LO_MASK 0xFFFFF #define MC_TZRAM_BASE_HI 0x2198 -#define TZRAM_BASE_HI_SHIFT 0 -#define TZRAM_BASE_HI_MASK 3 #define MC_TZRAM_SIZE 0x219C -#define TZRAM_SIZE_RANGE_4KB_SHIFT 27 - -#define MC_TZRAM_CARVEOUT_CFG 0x2190 -#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) -#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 -#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 - -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21B8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21BC -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C0 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21C4 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21C8 -#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21CC +#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 /******************************************************************************* * Tegra UART Controller constants |