diff options
| author | Jimmy Huang <jimmy.huang@mediatek.com> | 2015-11-16 13:44:31 +0800 |
|---|---|---|
| committer | Yidi Lin <yidi.lin@mediatek.com> | 2016-03-09 15:40:32 +0800 |
| commit | b99d961c7db6558d36e08d1656662226a8481a85 (patch) | |
| tree | 2112b400ce81e3418df3eb83f5fb3553653ae244 /plat/mediatek | |
| parent | 76d47fea7ec6a5d2049142dfcbea88cd175bd51e (diff) | |
mt8173: support big core PLL control in system suspend flow
This patch adds big core ARMPLL control in system suspend flow.
Change-Id: I27a45dbbb360f17ff0b524a125630358ee2277e2
Signed-off-by: Louis Yu <louis.yu@mediatek.com>
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Diffstat (limited to 'plat/mediatek')
| -rw-r--r-- | plat/mediatek/mt8173/drivers/rtc/rtc.c | 4 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/drivers/spm/spm_suspend.c | 30 | ||||
| -rw-r--r-- | plat/mediatek/mt8173/include/mt8173_def.h | 1 |
3 files changed, 31 insertions, 4 deletions
diff --git a/plat/mediatek/mt8173/drivers/rtc/rtc.c b/plat/mediatek/mt8173/drivers/rtc/rtc.c index e171863d..daaac42c 100644 --- a/plat/mediatek/mt8173/drivers/rtc/rtc.c +++ b/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -95,8 +95,8 @@ void rtc_bbpu_power_down(void) if (Writeif_unlock()) { RTC_Write(RTC_BBPU, bbpu); if (!Write_trigger()) - assert(1); + assert(0); } else { - assert(1); + assert(0); } } diff --git a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c index 6bf37f3a..843b5f9e 100644 --- a/plat/mediatek/mt8173/drivers/spm/spm_suspend.c +++ b/plat/mediatek/mt8173/drivers/spm/spm_suspend.c @@ -29,6 +29,9 @@ */ #include <bakery_lock.h> #include <debug.h> +#include <delay_timer.h> +#include <mmio.h> +#include <mt8173_def.h> #include <spm.h> #include <spm_suspend.h> @@ -38,8 +41,6 @@ * This driver controls the system power in system suspend flow. */ -#define WAIT_UART_ACK_TIMES 80 /* 80 * 10us */ - #define WAKE_SRC_FOR_SUSPEND \ (WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \ WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \ @@ -50,6 +51,13 @@ #define spm_is_wakesrc_invalid(wakesrc) \ (!!((unsigned int)(wakesrc) & 0xc0003803)) +#define ARMCA15PLL_CON0 (APMIXED_BASE + 0x200) +#define ARMCA15PLL_CON1 (APMIXED_BASE + 0x204) +#define ARMCA15PLL_PWR_CON0 (APMIXED_BASE + 0x20c) +#define ARMCA15PLL_PWR_ON (1U << 0) +#define ARMCA15PLL_ISO_EN (1U << 1) +#define ARMCA15PLL_EN (1U << 0) + const unsigned int spm_flags = SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS | SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS; @@ -293,8 +301,23 @@ static enum wake_reason_t go_to_sleep_after_wfi(void) return last_wr; } +static void bigcore_pll_on(void) +{ + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); +} + +static void bigcore_pll_off(void) +{ + mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); +} + void spm_system_suspend(void) { + bigcore_pll_off(); spm_lock_get(); go_to_sleep_before_wfi(spm_flags); set_suspend_ready(); @@ -308,4 +331,7 @@ void spm_system_suspend_finish(void) INFO("spm_wake_reason=%d\n", spm_wake_reason); clear_all_ready(); spm_lock_release(); + bigcore_pll_on(); + /* Add 20us delay for turning on PLL*/ + udelay(20); } diff --git a/plat/mediatek/mt8173/include/mt8173_def.h b/plat/mediatek/mt8173/include/mt8173_def.h index 71668c75..39bab149 100644 --- a/plat/mediatek/mt8173/include/mt8173_def.h +++ b/plat/mediatek/mt8173/include/mt8173_def.h @@ -46,6 +46,7 @@ #define RGU_BASE (IO_PHYS + 0x7000) #define PMIC_WRAP_BASE (IO_PHYS + 0xD000) #define MCUCFG_BASE (IO_PHYS + 0x200000) +#define APMIXED_BASE (IO_PHYS + 0x209000) #define TRNG_BASE (IO_PHYS + 0x20F000) #define MT_GIC_BASE (IO_PHYS + 0x220000) #define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) |