diff options
author | Igal Liberman <igall@marvell.com> | 2018-11-15 16:13:11 +0200 |
---|---|---|
committer | Konstantin Porotchkin <kostap@marvell.com> | 2018-12-04 14:09:44 +0200 |
commit | 55df84f974ea37abbb4f93f000f101f70cda5303 (patch) | |
tree | 74c33588cb82230e87c23d9d426d2be41a1049a8 /plat/marvell | |
parent | 9cb6751d5988fe62d10b809469d4f6ec082730c6 (diff) |
mvebu: cp110: avoid pcie power on/off sequence when called from Linux
In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
Read bit 21 of the mode, it marks if the caller is
the bootloader or the Linux Kernel.
Power off:
Check if the comphy was already configured to PCIe, if yes,
check if the caller is bootloader, if both conditions are true
(PCIe mode and called by Linux) - skip the power-off.
In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.
NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).
Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell')
-rw-r--r-- | plat/marvell/common/mrvl_sip_svc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c index 8bc633b1..bc4b6211 100644 --- a/plat/marvell/common/mrvl_sip_svc.c +++ b/plat/marvell/common/mrvl_sip_svc.c @@ -87,7 +87,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, SMC_RET1(handle, ret); case MV_SIP_COMPHY_POWER_OFF: /* x1: comphy_base, x2: comphy_index */ - ret = mvebu_cp110_comphy_power_off(x1, x2); + ret = mvebu_cp110_comphy_power_off(x1, x2, x3); SMC_RET1(handle, ret); case MV_SIP_COMPHY_PLL_LOCK: /* x1: comphy_base, x2: comphy_index */ |