diff options
| author | Justin Chadwell <justin.chadwell@arm.com> | 2019-07-03 14:04:33 +0100 |
|---|---|---|
| committer | Justin Chadwell <justin.chadwell@arm.com> | 2019-07-11 12:10:51 +0100 |
| commit | b19498b97b72879ad6ab746da9ee9a0020a413b1 (patch) | |
| tree | 85886a109728008aa5f34cfd142e4e6811e9c0e6 /plat/marvell | |
| parent | 21bde92ff6d20ef2d3a2651fd729a1579232313b (diff) | |
Update marvell platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Diffstat (limited to 'plat/marvell')
| -rw-r--r-- | plat/marvell/a8k/common/include/a8k_plat_def.h | 2 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/plat_ble_setup.c | 4 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/plat_pm.c | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index 8b7cd648..de803153 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -18,7 +18,7 @@ #define GWD_IIDR2_REV_ID_OFFSET 12 #define GWD_IIDR2_REV_ID_MASK 0xF #define GWD_IIDR2_CHIP_ID_OFFSET 20 -#define GWD_IIDR2_CHIP_ID_MASK (0xFFF << GWD_IIDR2_CHIP_ID_OFFSET) +#define GWD_IIDR2_CHIP_ID_MASK (0xFFFu << GWD_IIDR2_CHIP_ID_OFFSET) #define CHIP_ID_AP806 0x806 #define CHIP_ID_AP807 0x807 diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 0590cc0a..7f9e2427 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -77,13 +77,13 @@ /* VDD limit is 0.82V for all A3900 devices * AVS offsets are not the same as in A70x0 */ -#define AVS_A3900_CLK_VALUE ((0x80 << 24) | \ +#define AVS_A3900_CLK_VALUE ((0x80u << 24) | \ (0x2c2 << 13) | \ (0x2c2 << 3) | \ (0x1 << AVS_SOFT_RESET_OFFSET) | \ (0x1 << AVS_ENABLE_OFFSET)) /* VDD is 0.88V for 2GHz clock */ -#define AVS_A3900_HIGH_CLK_VALUE ((0x80 << 24) | \ +#define AVS_A3900_HIGH_CLK_VALUE ((0x80u << 24) | \ (0x2f5 << 13) | \ (0x2f5 << 3) | \ (0x1 << AVS_SOFT_RESET_OFFSET) | \ diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index e2575b13..d07601a5 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -93,7 +93,7 @@ enum CPU_ID { #define PWRC_CPUN_CR_ISO_ENABLE_MASK \ (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) #define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ - (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) + (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) #define CCU_B_PRCRN_REG(cpu_id) \ (MVEBU_REGS_BASE + 0x1A50 + \ @@ -253,7 +253,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr) /* 3. Assert power ready */ reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); - reg_val |= 0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET; + reg_val |= 0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET; mmio_write_32(PWRC_CPUN_CR_REG(cpu_id), reg_val); /* 4. Read & Validate power ready @@ -262,7 +262,7 @@ static int plat_marvell_cpu_powerup(u_register_t mpidr) do { reg_val = mmio_read_32(PWRC_CPUN_CR_REG(cpu_id)); exit_loop--; - } while (!(reg_val & (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) && + } while (!(reg_val & (0x1U << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET)) && exit_loop > 0); if (exit_loop <= 0) |