diff options
| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-20 15:33:27 +0800 |
|---|---|---|
| committer | Soby Mathew <soby.mathew@arm.com> | 2019-09-12 12:36:31 +0000 |
| commit | b90f207a1d386ec391bd3ea9eb403c4ad7b7551b (patch) | |
| tree | e7e7acdda3c1a7823b8ba8d7f14fe3f27bc1d64f /plat/intel | |
| parent | 2fc6ffc451c9af16e03eff51e779c33828e9ab07 (diff) | |
Invalidate dcache build option for bl2 entry at EL3
Some of the platform (ie. Agilex) make use of CCU IPs which will only be
initialized during bl2_el3_early_platform_setup. Any operation to the
cache beforehand will crash the platform. Hence, this will provide an
option to skip the data cache invalidation upon bl2 entry at EL3
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/platform.mk | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 5d20462b..d1ea6291 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -70,5 +70,6 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 +BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 USE_COHERENT_MEM := 1 |