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| author | Soby Mathew <soby.mathew@arm.com> | 2019-07-16 10:11:27 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-16 10:11:27 +0000 |
| commit | d0d0f171643a22bbc3d06f5b6dde40cc1d9d5d11 (patch) | |
| tree | 3bf8cd35df62b459af2c55ddb58628e15e1843b3 /plat/intel | |
| parent | dc150425c36c83edf48654424fcbbc98ee17acea (diff) | |
| parent | 93c690eba8ca67b06925d811ea87765215401385 (diff) | |
Merge changes from topic "jc/shift-overflow" into integration
* changes:
Enable -Wshift-overflow=2 to check for undefined shift behavior
Update base code to not rely on undefined overflow behaviour
Update hisilicon drivers to not rely on undefined overflow behaviour
Update synopsys drivers to not rely on undefined overflow behaviour
Update imx platform to not rely on undefined overflow behaviour
Update mediatek platform to not rely on undefined overflow behaviour
Update layerscape platform to not rely on undefined overflow behaviour
Update intel platform to not rely on undefined overflow behaviour
Update rockchip platform to not rely on undefined overflow behaviour
Update renesas platform to not rely on undefined overflow behaviour
Update meson platform to not rely on undefined overflow behaviour
Update marvell platform to not rely on undefined overflow behaviour
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/common/drivers/qspi/cadence_qspi.h | 2 | ||||
| -rw-r--r-- | plat/intel/soc/stratix10/include/s10_mailbox.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h index 4fb29223..cfef5858 100644 --- a/plat/intel/soc/common/drivers/qspi/cadence_qspi.h +++ b/plat/intel/soc/common/drivers/qspi/cadence_qspi.h @@ -34,7 +34,7 @@ #define CAD_QSPI_CFG_CS(x) (((x) << 11)) #define CAD_QSPI_CFG_ENABLE (1 << 0) #define CAD_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff -#define CAD_QSPI_CFG_IDLE (1 << 31) +#define CAD_QSPI_CFG_IDLE (1U << 31) #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd diff --git a/plat/intel/soc/stratix10/include/s10_mailbox.h b/plat/intel/soc/stratix10/include/s10_mailbox.h index 78db5205..554c2656 100644 --- a/plat/intel/soc/stratix10/include/s10_mailbox.h +++ b/plat/intel/soc/stratix10/include/s10_mailbox.h @@ -76,7 +76,7 @@ #define RECONFIG_STATUS_STATE 0 #define RECONFIG_STATUS_PIN_STATUS 2 #define RECONFIG_STATUS_SOFTFUNC_STATUS 3 -#define PIN_STATUS_NSTATUS (1 << 31) +#define PIN_STATUS_NSTATUS (1U << 31) #define SOFTFUNC_STATUS_SEU_ERROR (1 << 3) #define SOFTFUNC_STATUS_INIT_DONE (1 << 1) #define SOFTFUNC_STATUS_CONF_DONE (1 << 0) |