diff options
| author | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-16 17:07:42 +0800 |
|---|---|---|
| committer | Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> | 2019-08-19 18:19:04 +0800 |
| commit | 24d16a2e40dc6b38bd89faed20e7a1651d834871 (patch) | |
| tree | 3ec86fdcd8ff05eb92077325ca2b75d3802e0f21 /plat/intel | |
| parent | d1b6013d8485094d948e6b6039b8d119a907ecf8 (diff) | |
intel: agilex: HMC driver calculate DDR size
Driver will calculate DDR size instead of using hardcoded value
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
Diffstat (limited to 'plat/intel')
| -rw-r--r-- | plat/intel/soc/agilex/soc/agilex_memory_controller.c | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/plat/intel/soc/agilex/soc/agilex_memory_controller.c b/plat/intel/soc/agilex/soc/agilex_memory_controller.c index f09238c1..5f3cae7b 100644 --- a/plat/intel/soc/agilex/soc/agilex_memory_controller.c +++ b/plat/intel/soc/agilex/soc/agilex_memory_controller.c @@ -160,8 +160,6 @@ int init_hard_memory_controller(void) return status; } -/* mmio_clrbits_32(AGX_RSTMGR_BRGMODRST, AGX_RSTMGR_BRGMODRST_DDRSCH);*/ - status = mem_calibration(); if (status) { ERROR("DDR: Memory Calibration Failed\n"); @@ -169,7 +167,6 @@ int init_hard_memory_controller(void) } configure_hmc_adaptor_regs(); -/* configure_ddr_sched_ctrl_regs();*/ return 0; } @@ -359,16 +356,17 @@ void configure_hmc_adaptor_regs(void) mmio_write_32(AGX_MPFE_HMC_ADP(ADP_DRAMADDRWIDTH), data); /* Enable nonsecure access to DDR */ - mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, - AGX_DDR_SIZE - 1); - mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, - 0x1f); + data = get_physical_dram_size(); - mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, - AGX_DDR_SIZE - 1); + if (data < AGX_DDR_SIZE) + data = AGX_DDR_SIZE; - mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8)); + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMIT, data - 1); + mmio_write_32(AGX_NOC_FW_DDR_SCR_MPUREGION0ADDR_LIMITEXT, 0x1f); + mmio_write_32(AGX_NOC_FW_DDR_SCR_NONMPUREGION0ADDR_LIMIT, data - 1); + + mmio_write_32(AGX_SOC_NOC_FW_DDR_SCR_ENABLESET, BIT(0) | BIT(8)); /* ECC enablement */ data = mmio_read_32(AGX_MPFE_IOHMC_REG_CTRLCFG1); |