diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2018-06-05 16:13:45 +0800 |
---|---|---|
committer | Anson Huang <Anson.Huang@nxp.com> | 2018-06-19 10:24:32 +0800 |
commit | 0bc1830928616c850ce377c837f883bffe4caa3e (patch) | |
tree | a5b2fdbc663bcf8b62d384a0924da9e8a3249c43 /plat/imx/imx8qx/imx8qx_psci.c | |
parent | bd08def3c9b67a3b95cebdc4ad6433948fd2abbe (diff) |
Support for NXP's i.MX8QX SoC
NXP's i.MX8QX is an ARMv8 SoC with 4 Cortex-A35 cores and
system controller (Cortex-M4) inside, documentation can
be found in below link:
https://www.nxp.com/products/processors-and-microcontrollers/
applications-processors/i.mx-applications-processors/i.mx-8-processors:IMX8-SERIES
This patch adds support for booting up SMP linux kernel (v4.9).
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8qx/imx8qx_psci.c')
-rw-r--r-- | plat/imx/imx8qx/imx8qx_psci.c | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/plat/imx/imx8qx/imx8qx_psci.c b/plat/imx/imx8qx/imx8qx_psci.c new file mode 100644 index 00000000..47233dc8 --- /dev/null +++ b/plat/imx/imx8qx/imx8qx_psci.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <arch_helpers.h> +#include <debug.h> +#include <gicv3.h> +#include <mmio.h> +#include <plat_imx8.h> +#include <psci.h> +#include <sci/sci.h> +#include <stdbool.h> + +const static int ap_core_index[PLATFORM_CORE_COUNT] = { + SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 +}; + +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *target_state, + unsigned int ncpu) +{ + return 0; +} + +int imx_pwr_domain_on(u_register_t mpidr) +{ + int ret = PSCI_E_SUCCESS; + unsigned int cpu_id; + + cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + tf_printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); + + if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], + SC_PM_PW_MODE_ON) != SC_ERR_NONE) { + ERROR("core %d power on failed!\n", cpu_id); + ret = PSCI_E_INTERN_FAIL; + } + + if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], + true, BL31_BASE) != SC_ERR_NONE) { + ERROR("boot core %d failed!\n", cpu_id); + ret = PSCI_E_INTERN_FAIL; + } + + return ret; +} + +void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + plat_gic_pcpu_init(); + plat_gic_cpuif_enable(); +} + +int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) +{ + return PSCI_E_SUCCESS; +} + +static const plat_psci_ops_t imx_plat_psci_ops = { + .pwr_domain_on = imx_pwr_domain_on, + .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .validate_ns_entrypoint = imx_validate_ns_entrypoint, +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + imx_mailbox_init(sec_entrypoint); + *psci_ops = &imx_plat_psci_ops; + + return 0; +} |