imx: imx8qm: add domain suspend/resume support

Add domain suspend/resume support, Linux kernel
can "echo mem > /sys/power/state" to put system
into suspend mode, all CPUs and cluster will be
powered off and can be waked up if irq pending
in GIC, tested on i.MX8QM MEK board.

Since the power state has been implemented, switch
to use standard power state for CCI operations
instead of private cpu use count in i.MX8QM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

1 files changed, 69 insertions, 37 deletions

diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c
index f7def4a1..c37c39c4 100644
--- a/plat/imx/imx8qm/imx8qm_psci.c
+++ b/plat/imx/imx8qm/imx8qm_psci.c
@@ -15,17 +15,18 @@
 #include <sci/sci.h>
 #include <stdbool.h>
 
+#define CORE_PWR_STATE(state) \
+	((state)->pwr_domain_state[MPIDR_AFFLVL0])
+#define CLUSTER_PWR_STATE(state) \
+	((state)->pwr_domain_state[MPIDR_AFFLVL1])
+#define SYSTEM_PWR_STATE(state) \
+	((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
+
 const static int ap_core_index[PLATFORM_CORE_COUNT] = {
 	SC_R_A53_0, SC_R_A53_1, SC_R_A53_2,
 	SC_R_A53_3, SC_R_A72_0, SC_R_A72_1,
 };
 
-/* need to enable USE_COHERENT_MEM to avoid coherence issue */
-#if USE_COHERENT_MEM
-static unsigned int a53_cpu_on_number __section("tzfw_coherent_mem");
-static unsigned int a72_cpu_on_number __section("tzfw_coherent_mem");
-#endif
-
 int imx_pwr_domain_on(u_register_t mpidr)
 {
 	int ret = PSCI_E_SUCCESS;
@@ -37,9 +38,8 @@ int imx_pwr_domain_on(u_register_t mpidr)
 	tf_printf("imx_pwr_domain_on cluster_id %d, cpu_id %d\n", cluster_id, cpu_id);
 
 	if (cluster_id == 0) {
-		if (a53_cpu_on_number == 0)
-			sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_ON);
-
+		sc_pm_set_resource_power_mode(ipc_handle, SC_R_A53,
+			SC_PM_PW_MODE_ON);
 		if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id],
 			SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
 			ERROR("cluster0 core %d power on failed!\n", cpu_id);
@@ -52,9 +52,8 @@ int imx_pwr_domain_on(u_register_t mpidr)
 			ret = PSCI_E_INTERN_FAIL;
 		}
 	} else {
-		if (a72_cpu_on_number == 0)
-			sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_ON);
-
+		sc_pm_set_resource_power_mode(ipc_handle, SC_R_A72,
+			SC_PM_PW_MODE_ON);
 		if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id + 4],
 			SC_PM_PW_MODE_ON) != SC_ERR_NONE) {
 			ERROR(" cluster1 core %d power on failed!\n", cpu_id);
@@ -74,12 +73,9 @@ int imx_pwr_domain_on(u_register_t mpidr)
 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	uint64_t mpidr = read_mpidr_el1();
-	unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
 
-	if (cluster_id == 0 && a53_cpu_on_number++ == 0)
-		cci_enable_snoop_dvm_reqs(0);
-	if (cluster_id == 1 && a72_cpu_on_number++ == 0)
-		cci_enable_snoop_dvm_reqs(1);
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+		cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
 
 	plat_gic_pcpu_init();
 	plat_gic_cpuif_enable();
@@ -92,22 +88,41 @@ void imx_pwr_domain_off(const psci_power_state_t *target_state)
 	unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
 
 	plat_gic_cpuif_disable();
-	if (cluster_id == 0) {
-		sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
-			SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE);
-		if (--a53_cpu_on_number == 0)
-			cci_disable_snoop_dvm_reqs(0);
-	} else {
-		sc_pm_req_cpu_low_power_mode(ipc_handle,
-			ap_core_index[cpu_id + 4],
-			SC_PM_PW_MODE_OFF,
-			SC_PM_WAKE_SRC_NONE);
-		if (--a72_cpu_on_number == 0)
-			cci_disable_snoop_dvm_reqs(1);
-	}
+	sc_pm_req_cpu_low_power_mode(ipc_handle,
+		ap_core_index[cpu_id + cluster_id * 4],
+		SC_PM_PW_MODE_OFF,
+		SC_PM_WAKE_SRC_NONE);
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE)
+		cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
 	tf_printf("turn off cluster:%d core:%d\n", cluster_id, cpu_id);
 }
 
+void imx_domain_suspend(const psci_power_state_t *target_state)
+{
+	u_register_t mpidr = read_mpidr_el1();
+	unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
+	unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
+
+	plat_gic_cpuif_disable();
+
+	cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
+
+	sc_pm_set_cpu_resume_addr(ipc_handle,
+		ap_core_index[cpu_id + cluster_id * 4], BL31_BASE);
+	sc_pm_req_cpu_low_power_mode(ipc_handle,
+		ap_core_index[cpu_id + cluster_id * 4],
+		SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC);
+}
+
+void imx_domain_suspend_finish(const psci_power_state_t *target_state)
+{
+	u_register_t mpidr = read_mpidr_el1();
+
+	cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr));
+
+	plat_gic_cpuif_enable();
+}
+
 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint)
 {
 	return PSCI_E_SUCCESS;
@@ -117,6 +132,10 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
 	.pwr_domain_on = imx_pwr_domain_on,
 	.pwr_domain_on_finish = imx_pwr_domain_on_finish,
 	.pwr_domain_off = imx_pwr_domain_off,
+	.pwr_domain_suspend = imx_domain_suspend,
+	.pwr_domain_suspend_finish = imx_domain_suspend_finish,
+	.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
+	.validate_power_state = imx_validate_power_state,
 	.validate_ns_entrypoint = imx_validate_ns_entrypoint,
 	.system_off = imx_system_off,
 	.system_reset = imx_system_reset,
@@ -125,16 +144,29 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const plat_psci_ops_t **psci_ops)
 {
-	uint64_t mpidr = read_mpidr_el1();
-	unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr);
-
 	imx_mailbox_init(sec_entrypoint);
 	*psci_ops = &imx_plat_psci_ops;
 
-	if (cluster_id == 0)
-		a53_cpu_on_number++;
-	else
-		a72_cpu_on_number++;
+	/* Request low power mode for cluster/cci, only need to do once */
+	sc_pm_req_low_power_mode(ipc_handle, SC_R_A72, SC_PM_PW_MODE_OFF);
+	sc_pm_req_low_power_mode(ipc_handle, SC_R_A53, SC_PM_PW_MODE_OFF);
+	sc_pm_req_low_power_mode(ipc_handle, SC_R_CCI, SC_PM_PW_MODE_OFF);
+
+	/* Request RUN and LP modes for DDR, system interconnect etc. */
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53,
+		SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72,
+		SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53,
+		SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72,
+		SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A53,
+		SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON,
+		SC_PM_PW_MODE_STBY);
+	sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A72,
+		SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON,
+		SC_PM_PW_MODE_STBY);
 
 	return 0;
 }