diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-10-16 23:41:31 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:39 +0300 |
| commit | 56537aef3bbf604e7a5e8e04f3f61198d4df8555 (patch) | |
| tree | f99612ac436276497de09118be74c9cb16e84eea /plat/imx/imx8qm | |
| parent | 1ca2c3e540431f41dda3b809779e1da08d3a8375 (diff) | |
imx8qm: add suspend/resume support
Add suspend/resume support with all CPUs power down.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8qm')
| -rw-r--r-- | plat/imx/imx8qm/imx8qm_psci.c | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/plat/imx/imx8qm/imx8qm_psci.c b/plat/imx/imx8qm/imx8qm_psci.c index 10657596..fc36216f 100644 --- a/plat/imx/imx8qm/imx8qm_psci.c +++ b/plat/imx/imx8qm/imx8qm_psci.c @@ -190,12 +190,37 @@ void imx_cpu_standby(plat_local_state_t cpu_state) void imx_domain_suspend(const psci_power_state_t *target_state) { - /* TODO */ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + plat_gic_cpuif_disable(); + + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + if (cluster_id == 0) { + sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], 0x080000000); + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_OFF); + } else { + sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id + 4], 0x080000000); + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id + 4], SC_PM_PW_MODE_OFF); + } } void imx_domain_suspend_finish(const psci_power_state_t *target_state) { - /* TODO */ + u_register_t mpidr = read_mpidr_el1(); + unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); + unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); + + if (cluster_id == 0) + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], SC_PM_PW_MODE_ON); + else + sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id + 4], SC_PM_PW_MODE_ON); + + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); + + plat_gic_cpuif_enable(); } void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) |