diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-08-16 22:09:45 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:39 +0300 |
| commit | f94a57297f6714785976dc44c6f566e15efeb264 (patch) | |
| tree | b61e9bd32fd949a15d30ae161e43f32660c713c2 /plat/imx/imx8mq | |
| parent | aabf9533ef1008f92b65be0608d380d5a513f983 (diff) | |
imx8mq: enable PU power domain
- USB PHY reset bit in SRC needs to be clear before
doing USB PHY power gating in GPC, only needs to
do once;
- Need to handle GPC_PU_PWRHSK during power up/down;
- Enable GPC pu power gate support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/gpc.c | 31 | ||||
| -rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 4 |
2 files changed, 29 insertions, 6 deletions
diff --git a/plat/imx/imx8mq/gpc.c b/plat/imx/imx8mq/gpc.c index 96848f1d..51774dd8 100644 --- a/plat/imx/imx8mq/gpc.c +++ b/plat/imx/imx8mq/gpc.c @@ -444,8 +444,6 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on) uint32_t val; uintptr_t reg; - return; - /* * PCIE1 and PCIE2 share the same reset signal, if we power down * PCIE2, PCIE1 will be hold in reset too. @@ -464,6 +462,23 @@ static void imx_gpc_pm_domain_enable(uint32_t domain_id, uint32_t on) if (domain_id == 10 && !on && !is_pcie1_power_down) return; + /* need to handle GPC_PU_PWRHSK */ + /* GPU */ + if (domain_id == 4 && !on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) & ~0x40); + if (domain_id == 4 && on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) | 0x40); + /* VPU */ + if (domain_id == 5 && !on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) & ~0x20); + if (domain_id == 5 && on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) | 0x20); + /* DISPLAY */ + if (domain_id == 7 && !on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) & ~0x10); + if (domain_id == 7 && on) + mmio_write_32(0x303a01fc, mmio_read_32(0x303a01fc) | 0x10); + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); reg = IMX_GPC_BASE + (on ? 0xf8 : 0x104); @@ -525,6 +540,18 @@ void imx_gpc_init(void) val &= ~(1 << 31); /* TODO if M4 is not enabled, clear more SLPCR bits */ mmio_write_32(IMX_GPC_BASE + GPC_SLPCR, val); + + /* + * USB PHY power up needs to make sure RESET bit in SRC is clear, + * otherwise, the PU power up bit in GPC will NOT self-cleared. + * only need to do it once. + */ + val = mmio_read_32(0x30390020); + val &= ~0x1; + mmio_write_32(0x30390020, val); + val = mmio_read_32(0x30390024); + val &= ~0x1; + mmio_write_32(0x30390024, val); } int imx_gpc_handler(uint32_t smc_fid, diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index 5b11beed..ac5067b2 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -171,10 +171,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_32(0x32df004c, 0x0); mmio_write_32(0x32df0050, 0x0); - mmio_write_32(0x303a00ec, 0x0000ffff); - /* Power up VPU, DISP, GPU etc */ - mmio_write_32(0x303a00f8, 0x3fef); - #if DEBUG_CONSOLE console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, IMX_CONSOLE_BAUDRATE); |