diff options
| author | Aymen Sghaier <aymen.sghaier@nxp.com> | 2017-11-21 10:00:34 +0100 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:40 +0300 |
| commit | f4ec82775b77039912e0b369e808a49bfad7b9c4 (patch) | |
| tree | 4b65da09f06c6e6d0b050c48e5a6be2683452b0c /plat/imx/imx8mq | |
| parent | 5ca8d95b1797f2e169deec5029bf3ac1c41c5c85 (diff) | |
imx8mq: disable default rdc and csu configurations to fix boot block
Enabling the default csu configuration lead to block boot on
testing boards.
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 25 |
1 files changed, 6 insertions, 19 deletions
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index f209b8fc..3f33eaef 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -60,23 +60,6 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; -/* set RDC settings */ -static void bl31_imx_rdc_setup(void) -{ - NOTICE("RDC imx_rdc_set_peripherals default \n"); - imx_rdc_set_peripherals_default(); - NOTICE("RDC imx_rdc_set_masters default \n"); - imx_rdc_set_masters_default(); -} - -static void bl31_imx_csu_setup(void) -{ - NOTICE("Configuring CSU slaves ... \n"); - csu_set_default_slaves_modes(); - NOTICE("Configuring CSU secure access ... \n"); - csu_set_default_secure_configs(); -} - /* get SPSR for BL33 entry */ static uint32_t get_spsr_for_bl33_entry(void) { @@ -146,6 +129,12 @@ void bl31_tzc380_setup(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { + int i; + /* enable CSU NS access permission */ + for (i = 0; i < 64; i++) { + mmio_write_32(0x303e0000 + i * 4, 0xffffffff); + } + /* config the AIPSTZ1 */ mmio_write_32(0x301f0000, 0x77777777); mmio_write_32(0x301f0004, 0x77777777); @@ -208,8 +197,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.args.arg2 = 0x2000000; #endif bl31_tzc380_setup(); - bl31_imx_csu_setup(); - bl31_imx_rdc_setup(); } void bl31_plat_arch_setup(void) |