diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2017-11-03 18:39:24 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:40 +0300 |
| commit | bf35eec4a53aa16bc6b03caa909930bbbd96c539 (patch) | |
| tree | 6ef2fc2d4cf1dbbb2acad54177ff94448cc34b27 /plat/imx/imx8mq | |
| parent | 7280cd36cc7ca6e3a3703ee3c03c9c582d937205 (diff) | |
imx: imx8mq: add SOC info SIP support for i.MX8MQ
i.MX8MQ does NOT update revision info in ANATOP_DIGPROG
register, so the revision info needs to read from ROM,
for security reason, this needs to be done in ATF, so
add this SIP support for kernel.
The A0 chip's ROM version is located at 0x800, and B0
chip is located at 0x83c.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 2 | ||||
| -rw-r--r-- | plat/imx/imx8mq/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/imx/imx8mq/src.c | 24 |
3 files changed, 27 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index e61ab5b7..176283c0 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -206,6 +206,8 @@ void bl31_plat_arch_setup(void) MT_MEMORY | MT_RO); mmap_add_region(IMX_BOOT_UART_BASE, IMX_BOOT_UART_BASE, 0x1000, MT_DEVICE | MT_RW); + mmap_add_region(IMX_ROM_BASE, IMX_ROM_BASE, + 0x1000, MT_DEVICE | MT_RW); /* map the AIPS1 */ mmap_add_region(IMX_AIPS1_BASE, IMX_AIPS1_BASE, 0x200000, MT_DEVICE | MT_RW); mmap_add_region(PLAT_GICD_BASE, PLAT_GICD_BASE, 0x80000, diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h index b3ea3f3d..faff2021 100644 --- a/plat/imx/imx8mq/include/platform_def.h +++ b/plat/imx/imx8mq/include/platform_def.h @@ -54,6 +54,7 @@ #define IMX_DDRC_BASE 0x3d400000 #define IMX_DDRPHY_BASE 0x3c000000 #define IMX_DDR_IPS_BASE 0x3d000000 +#define IMX_ROM_BASE 0x0 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c index 4fa0e2c3..25382dd0 100644 --- a/plat/imx/imx8mq/src.c +++ b/plat/imx/imx8mq/src.c @@ -21,6 +21,11 @@ #define SRC_SCR_M4_ENABLE_MASK (1 << 3) #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 #define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 0) + +#define DIGPROG 0x6c +#define SW_INFO_A0 0x800 +#define SW_INFO_B0 0x83C + int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3) { @@ -43,3 +48,22 @@ int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, return 0; } + +int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, + u_register_t x3) +{ + uint32_t val; + uint32_t rom_version; + + val = mmio_read_32(IMX_ANAMIX_BASE + DIGPROG); + rom_version = mmio_read_32(IMX_ROM_BASE + SW_INFO_A0); + if (rom_version != 0x10) { + rom_version = mmio_read_32(IMX_ROM_BASE + SW_INFO_B0); + if (rom_version >= 0x20) { + val &= ~0xff; + val |= rom_version; + } + } + + return val; +} |