MLK-18343-2: plat: imx8mm: add support for RDC and CSU

move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm

Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>

5 files changed, 2 insertions, 919 deletions

diff --git a/plat/imx/imx8mq/imx_csu.c b/plat/imx/imx8mq/imx_csu.c
deleted file mode 100644
index 85c1caf8..00000000
--- a/plat/imx/imx8mq/imx_csu.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <debug.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <platform_def.h>
-#include <utils_def.h>
-#include <mmio.h>
-#include <imx_csu.h>
-
-#define CSU_HP0_OFFSET		(0x200)
-#define CSU_HP1_OFFSET		(0x204)
-#define CSU_SA_OFFSET		(0x218)
-#define CSU_HPC0_OFFSET		(0x358)
-#define CSU_HPC1_OFFSET		(0x35C)
-
-
-/* Default CSU slaves CSLn settings */
-static struct csu_slave_conf csu_def_csl_conf[] = {
-	{CSU_CSLn_GPIO1, CSU_RW, 0},
-	{CSU_CSLn_GPIO2, CSU_RW, 0},
-	{CSU_CSLn_GPIO3, CSU_RW, 0},
-	{CSU_CSLn_GPIO4, CSU_RW, 0},
-#if defined (CSU_RDC_TEST)
-	{CSU_CSLn_GPIO5, CSU_SSRW, 0},
-#else
-	{CSU_CSLn_GPIO5, CSU_RW, 0},
-#endif
-	{CSU_CSLn_Reserved1, CSU_RW, 0},
-	{CSU_CSLn_ANA_TSENSOR, CSU_RW, 0},
-	{CSU_CSLn_ANA_OSC, CSU_RW, 0},
-	{CSU_CSLn_WDOG1, CSU_RW, 0},
-	{CSU_CSLn_WDOG2, CSU_RW, 0},
-	{CSU_CSLn_WDOG3, CSU_RW, 0},
-	{CSU_CSLn_SDMA2, CSU_RW, 0},
-	{CSU_CSLn_GPT1, CSU_RW, 0},
-	{CSU_CSLn_GPT2, CSU_RW, 0},
-	{CSU_CSLn_GPT3, CSU_RW, 0},
-	{CSU_CSLn_ROMCP, CSU_RW, 0},
-	{CSU_CSLn_LCDIF, CSU_RW, 0},
-	{CSU_CSLn_IOMUXC, CSU_RW, 0},
-	{CSU_CSLn_IOMUXC_GPR, CSU_RW, 0},
-	{CSU_CSLn_OCOTP_CTRL, CSU_RW, 0},
-	{CSU_CSLn_ANATOP_PLL, CSU_RW, 0},
-	{CSU_CSLn_SNVS_HP, CSU_RW, 0},
-	{CSU_CSLn_CCM, CSU_RW, 0},
-	{CSU_CSLn_SRC, CSU_RW, 0},
-	{CSU_CSLn_GPC, CSU_RW, 0},
-	{CSU_CSLn_SEMAPHORE1, CSU_RW, 0},
-	{CSU_CSLn_SEMAPHORE2, CSU_RW, 0},
-	{CSU_CSLn_RDC, CSU_RW, 0},
-	{CSU_CSLn_CSU, CSU_RW, 0},
-	{CSU_CSLn_MST0, CSU_RW, 0},
-	{CSU_CSLn_MST1, CSU_RW, 0},
-	{CSU_CSLn_MST2, CSU_RW, 0},
-	{CSU_CSLn_MST3, CSU_RW, 0},
-	{CSU_CSLn_HDMI_SEC, CSU_RW, 0},
-	{CSU_CSLn_PWM1, CSU_RW, 0},
-	{CSU_CSLn_PWM2, CSU_RW, 0},
-	{CSU_CSLn_PWM3, CSU_RW, 0},
-	{CSU_CSLn_PWM4, CSU_RW, 0},
-	{CSU_CSLn_SysCounter_RD, CSU_RW, 0},
-	{CSU_CSLn_SysCounter_CMP, CSU_RW, 0},
-	{CSU_CSLn_SysCounter_CTRL, CSU_RW, 0},
-	{CSU_CSLn_HDMI_CTRL, CSU_RW, 0},
-	{CSU_CSLn_GPT6, CSU_RW, 0},
-	{CSU_CSLn_GPT5, CSU_RW, 0},
-	{CSU_CSLn_GPT4, CSU_RW, 0},
-	{CSU_CSLn_TZASC, CSU_RW, 0},
-	{CSU_CSLn_MTR, CSU_RW, 0},
-	{CSU_CSLn_PERFMON1, CSU_RW, 0},
-	{CSU_CSLn_PERFMON2, CSU_RW, 0},
-	{CSU_CSLn_PLATFORM_CTRL, CSU_RW, 0},
-	{CSU_CSLn_QoSC, CSU_RW, 0},
-	{CSU_CSLn_MIPI_PHY, CSU_RW, 0},
-	{CSU_CSLn_MIPI_DSI, CSU_RW, 0},
-	{CSU_CSLn_I2C1, CSU_RW, 0},
-	{CSU_CSLn_I2C2, CSU_RW, 0},
-	{CSU_CSLn_I2C3, CSU_RW, 0},
-	{CSU_CSLn_I2C4, CSU_RW, 0},
-	{CSU_CSLn_UART4, CSU_RW, 0},
-	{CSU_CSLn_MIPI_CSI1, CSU_RW, 0},
-	{CSU_CSLn_MIPI_CSI_PHY1, CSU_RW, 0},
-	{CSU_CSLn_CSI1, CSU_RW, 0},
-	{CSU_CSLn_MU_A, CSU_RW, 0},
-	{CSU_CSLn_MU_B, CSU_RW, 0},
-	{CSU_CSLn_SEMAPHORE_HS, CSU_RW, 0},
-	{CSU_CSLn_SAI1, CSU_RW, 0},
-	{CSU_CSLn_SAI6, CSU_RW, 0},
-	{CSU_CSLn_SAI5, CSU_RW, 0},
-	{CSU_CSLn_SAI4, CSU_RW, 0},
-	{CSU_CSLn_USDHC1, CSU_RW, 0},
-	{CSU_CSLn_USDHC2, CSU_RW, 0},
-	{CSU_CSLn_MIPI_CSI2, CSU_RW, 0},
-	{CSU_CSLn_MIPI_CSI_PHY2, CSU_RW, 0},
-	{CSU_CSLn_CSI2, CSU_RW, 0},
-	{CSU_CSLn_QSPI, CSU_RW, 0},
-	{CSU_CSLn_SDMA1, CSU_RW, 0},
-	{CSU_CSLn_ENET1, CSU_RW, 0},
-	{CSU_CSLn_SPDIF1, CSU_RW, 0},
-	{CSU_CSLn_ECSPI1, CSU_RW, 0},
-	{CSU_CSLn_ECSPI2, CSU_RW, 0},
-	{CSU_CSLn_ECSPI3, CSU_RW, 0},
-	{CSU_CSLn_UART1, CSU_RW, 0},
-	{CSU_CSLn_UART3, CSU_RW, 0},
-	{CSU_CSLn_UART2, CSU_RW, 0},
-	{CSU_CSLn_SPDIF2, CSU_RW, 0},
-	{CSU_CSLn_SAI2, CSU_RW, 0},
-	{CSU_CSLn_SAI3, CSU_RW, 0},
-	{CSU_CSLn_SPBA1, CSU_RW, 0},
-	{CSU_CSLn_MOD_EN3, CSU_RW, 0},
-	{CSU_CSLn_MOD_EN0, CSU_RW, 0},
-	{CSU_CSLn_CAAM, CSU_RW, 0},
-	{CSU_CSLn_DDRC_SEC, CSU_RW, 0},
-	{CSU_CSLn_GIC_EXSC, CSU_RW, 0},
-	{CSU_CSLn_USB_EXSC, CSU_RW, 0},
-	{CSU_CSLn_OCRAM_TZ, CSU_RW, 0},
-	{CSU_CSLn_OCRAM_S_TZ, CSU_RW, 0},
-	{CSU_CSLn_VPU_SEC, CSU_RW, 0},
-	{CSU_CSLn_DAP_EXSC, CSU_RW, 0},
-	{CSU_CSLn_ROMCP_SEC, CSU_RW, 0},
-	{CSU_CSLn_APBHDMA_SEC, CSU_RW, 0},
-	{CSU_CSLn_M4_SEC, CSU_RW, 0},
-	{CSU_CSLn_QSPI_SEC, CSU_RW, 0},
-	{CSU_CSLn_GPU_EXSC, CSU_RW, 0},
-	{CSU_CSLn_Internal1, CSU_RW, 0},
-	{CSU_CSLn_Internal2, CSU_RW, 0},
-	{CSU_CSLn_Internal3, CSU_RW, 0},
-	{CSU_CSLn_Internal4, CSU_RW, 0},
-	{CSU_CSLn_Internal5, CSU_RW, 0},
-	{CSU_CSLn_Internal6, CSU_RW, 0},
-};
-
-/* Default Secure Access configuration */
-static struct csu_sa_conf sa_def_configs[] = {
-	{CSU_SA_VPU, 1, 1},
-	{CSU_SA_GPU, 1, 1},
-	{CSU_SA_DCSS, 1, 1},
-};
-
-void csu_set_slave_index_mode(enum csu_csln_idx index,
-			uint16_t mode, uint8_t lock)
-{
-	uintptr_t reg;
-	uint32_t tmp;
-	uint16_t read_mode;
-	uint8_t read_lock = 0;
-
-	/* Check if CSLn is locked or the value is same as written */
-	csu_get_slave_index_mode(index, &read_mode, &read_lock);
-	if (read_lock) {
-		NOTICE("CSU CSLn(%d) already locked with mode:0x%x\n", index, read_mode);
-		return;
-	}
-	if (read_mode == mode) {
-		NOTICE("CSU CSLn(%d) mode 0x%x already written\n", index, read_mode);
-		return;
-	}
-	reg = (uintptr_t)(IMX_CSU_BASE + (index / 2) * 4);
-	tmp = mmio_read_32(reg);
-
-	if (lock)
-		mode |= 1 << 8;
-
-	if (index % 2) {
-		tmp &= 0x0000ffff;
-		tmp |= mode << 16;
-	} else {
-		tmp &= 0xffff0000;
-		tmp |= mode;
-	}
-	mmio_write_32(reg, tmp);
-}
-
-void csu_get_slave_index_mode(enum csu_csln_idx index,
-			uint16_t *mode, uint8_t *lock)
-{
-	uintptr_t reg;
-	uint32_t tmp;
-
-	reg = (uintptr_t)(IMX_CSU_BASE + (index / 2) * 4);
-	tmp = mmio_read_32(reg);
-	if (index % 2)
-		tmp = tmp >> 16;
-
-	tmp &= 0x1ff;
-
-	*mode = tmp & 0xff;
-	*lock = tmp >> 8;	
-}
-
-void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count)
-{
-	int i;
-
-	for (i = 0; i < count; i++) {
-		csu_set_slave_index_mode(csu_config[i].index, csu_config[i].mode, csu_config[i].lock);
-	}
-}
-
-void csu_set_default_slaves_modes(void)
-{
-	NOTICE("csu_set_default_slaves_modes: count = %d \n", (int)ARRAY_SIZE(csu_def_csl_conf));
-	csu_set_slaves_modes(csu_def_csl_conf, (uint32_t)ARRAY_SIZE(csu_def_csl_conf));
-}
-
-void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable,
-			uint8_t set_control, uint8_t lock)
-{
-	uint32_t tmp, value;
-	uintptr_t reg;
-
-	if (index < 16){
-		reg = (uintptr_t)(IMX_CSU_BASE + CSU_HP0_OFFSET);
-		tmp = mmio_read_32(reg);
-		value = 0x3 << (index * 2);
-		tmp &= ~value;
-		value = (lock * 2 | enable) << (index * 2);
-		tmp |= value;
-		mmio_write_32(reg, tmp);
-		if (set_control) {
-			reg = (uintptr_t)(IMX_CSU_BASE + CSU_HPC0_OFFSET);
-			tmp = mmio_read_32(reg);
-			value = (lock * 2 | set_control) << (index * 2);
-			tmp &= ~value;
-			tmp |= value;
-			mmio_write_32(reg, tmp);
-		}
-	} else {
-		reg = (uintptr_t)(IMX_CSU_BASE + CSU_HP1_OFFSET);
-		mmio_write_32(reg,lock * 2 | enable);
-		if (set_control) {
-			reg = (uintptr_t)(IMX_CSU_BASE + CSU_HPC1_OFFSET);
-			mmio_write_32(reg,lock * 2 | set_control);
-		}
-	}
-}
-
-void csu_set_sa_index_config(enum csu_sa_idx index,
-			uint8_t enable, uint8_t lock)
-{
-	uint32_t tmp, value;
-	uintptr_t reg;
-
-	reg = (uintptr_t)(IMX_CSU_BASE + CSU_SA_OFFSET);
-	tmp = mmio_read_32((uintptr_t)reg);
-	value = 0x3 << (index * 2);
-	tmp &= ~value;
-	value = (lock * 2 | enable) << (index * 2);
-	tmp |= value;
-	mmio_write_32(reg, tmp);
-}
-
-void csu_get_sa_index_config(enum csu_sa_idx index,
-			uint8_t *enable, uint8_t *lock)
-{
-	uint32_t tmp;
-	uintptr_t reg;
-
-	reg = (uintptr_t)(IMX_CSU_BASE + CSU_SA_OFFSET);
-	tmp = mmio_read_32((uintptr_t)reg);
-	*enable = (tmp >> (index * 2)) & 1;
-	*lock = (tmp >> (index * 2 + 1)) & 1;
-}
-
-void csu_set_sa_configs(struct csu_sa_conf *sa_conf,  uint32_t count)
-{
-	int i;
-
-	for (i = 0; i < count; i++)
-		csu_set_sa_index_config(sa_conf[i].index,
-			sa_conf[i].enable, sa_conf[i].lock);
-}
-
-void csu_set_default_secure_configs(void)
-{
-	csu_set_sa_configs(sa_def_configs, (uint32_t)ARRAY_SIZE(sa_def_configs));
-}
-
-#if defined (CSU_RDC_TEST)
-void csu_test(void)
-{
-	csu_set_default_slaves_modes();
-}
-#endif
diff --git a/plat/imx/imx8mq/imx_rdc.c b/plat/imx/imx8mq/imx_rdc.c
deleted file mode 100644
index 1929c99b..00000000
--- a/plat/imx/imx8mq/imx_rdc.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <debug.h>
-#include <errno.h>
-#include <stdlib.h>
-#include <stdint.h>
-#include <platform_def.h>
-#include <utils_def.h>
-#include <imx_rdc.h>
-#include <mmio.h>
-
-/*
- * Read RDC settings for one peripheral
- * read the given domains field and lock bit
- * for the given PDAP index [0..118]
- */
-int imx_rdc_get_pdap(struct rdc_pdap_conf *p)
-{
-	struct imx_rdc_regs *imx_rdc = (struct imx_rdc_regs *)IMX_RDC_BASE;
-	uint32_t reg = 0;
-
-	reg = mmio_read_32((uintptr_t)&imx_rdc->pdap[p->index]);
-	p->lock = (reg & RDC_PDAP_LCK_MASK) >> RDC_PDAP_LCK_SHIFT;
-	p->domains = reg & 0xFF;
-
-	return 0;
-}
-
-/*
- * Write RDC settings for one peripheral
- * Check before write if is already locked then skip
- */
-int imx_rdc_set_pdap(struct rdc_pdap_conf *p)
-{
-	struct imx_rdc_regs *imx_rdc = (struct imx_rdc_regs *)IMX_RDC_BASE;
-	struct rdc_pdap_conf r;
-	uint32_t i, reg = 0;
-	uint8_t multi_domain = 0;
-
-	/* Check if locked */
-	r.index = p->index;
-	imx_rdc_get_pdap(&r);
-	if (r.lock) {
-		WARN("RDC_PDAPn %d is already locked \n", p->index);
-		return -ENOENT;
-	}
-
-	/* Check if no domain assigned */
-	if (p->domains == 0)
-		return -EINVAL;
-	reg |= p->domains;
-
-	/* Check if SREQ is needed */
-	for (i = 0; i < 7; i += 2)
-		multi_domain += ((p->domains >> i) & 0x3) ? 1 : 0;
-	if (multi_domain > 1)
-		reg |= RDC_PDAP_SREQ_MASK;
-	/* Setup Lock from input */
-	reg |= p->lock << RDC_PDAP_LCK_SHIFT;
-	mmio_write_32((uintptr_t)&imx_rdc->pdap[p->index], reg);
-
-	return 0;
-}
-
-/*
- * Setup RDC settings for multiple peripherals
- */
-int imx_rdc_set_peripherals(struct rdc_pdap_conf *peripherals_list,
-				uint32_t count)
-{
-	int i, ret;
-
-	for (i = 0; i < count; i++) {
-		ret = imx_rdc_set_pdap(&peripherals_list[i]);
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-}
-
-/*
- * Read RDC setting for one master
- * For the given index in p.index it returns the lock bit
- * and the domain field into p structure.
- */
-int imx_rdc_get_mda(struct rdc_mda_conf *p)
-{
-	struct imx_rdc_regs *imx_rdc = (struct imx_rdc_regs *)IMX_RDC_BASE;
-	uint32_t reg = 0;
-
-	reg = mmio_read_32((uintptr_t)&imx_rdc->mda[p->index]);
-	p->domain = reg & RDC_MDA_DID_MASK;
-	p->lock = (reg & RDC_MDA_LCK_MASK) >> RDC_MDA_LCK_SHIFT;
-	return 0;
-}
-
-/*
- * Write RDC setting for one master
- */
-int imx_rdc_set_mda(struct rdc_mda_conf *p)
-{
-	struct imx_rdc_regs *imx_rdc = (struct imx_rdc_regs *)IMX_RDC_BASE;
-	struct rdc_mda_conf r;
-	uint32_t reg = 0;
-	int ret = 0;
-
-	/* Check if it is locked */
-	r.index = p->index;
-	imx_rdc_get_mda(&r);
-	if (!r.lock) {
-	reg = (p->domain & RDC_MDA_DID_MASK)
-		| ((p->lock << RDC_MDA_LCK_SHIFT) & RDC_MDA_LCK_MASK);
-	NOTICE("imx_rdc_setup_mda(): write addr=0x%p, reg=0x%x\n",
-			&imx_rdc->mda[p->index], reg);
-	mmio_write_32((uintptr_t)&imx_rdc->mda[p->index], reg);
-	} else {
-		WARN("RDC_MDAn %d is already locked \n", p->index);
-		ret = -ENOENT;
-	}
-
-	return ret;
-}
-
-/*
- * Setup RDC settings for multiple masters
- */
-int imx_rdc_set_masters(struct rdc_mda_conf *masters_list, uint32_t count)
-{
-	int i, ret;
-
-	for (i = 0; i < count; i++) {
-		ret = imx_rdc_set_mda(&masters_list[i]);
-		if (ret)
-			break;
-	}
-
-	return ret;
-}
-
-#if defined (CSU_RDC_TEST)
-/* Default peripherals settings as an example */
-static struct rdc_pdap_conf periph_config[] = {
-	{RDC_PDAP_GPIO4, 0x30, 0},
-};
-
-
-/* Default masters settings as an example */
-static struct rdc_mda_conf masters_config[] = {
-	{RDC_MDA_A53, 0, 0},
-};
-#else
-/* Default peripherals settings as an example */
-static struct rdc_pdap_conf periph_config[] = {
-	{RDC_PDAP_GPIO1, 0x3, 0},
-	{RDC_PDAP_GPIO2, 0x3, 0},
-	{RDC_PDAP_GPIO3, 0x3, 0},
-	{RDC_PDAP_GPIO4, 0x3, 0},
-	{RDC_PDAP_GPIO5, 0x3, 0},
-};
-
-/* Default masters settings as an example */
-static struct rdc_mda_conf masters_config[] = {
-	{RDC_MDA_A53, 0, 0},
-	{RDC_MDA_CAAM, 0, 0},
-};
-#endif
-void imx_rdc_set_peripherals_default(void)
-{
-	imx_rdc_set_peripherals(periph_config, ARRAY_SIZE(periph_config));
-}
-
-void imx_rdc_set_masters_default(void)
-{
-	imx_rdc_set_masters(masters_config, ARRAY_SIZE(masters_config));
-}
-#if defined (CSU_RDC_TEST)
-void rdc_test(void)
-{
-	imx_rdc_set_peripherals_default();
-	imx_rdc_set_masters_default();
-}
-#endif
diff --git a/plat/imx/imx8mq/include/imx_csu.h b/plat/imx/imx8mq/include/imx_csu.h
deleted file mode 100644
index a4ae9abd..00000000
--- a/plat/imx/imx8mq/include/imx_csu.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __IMX_CSU_H__
-#define __IMX_CSU_H__
-
-enum csu_mode {
-	CSU_NSR = 0x08,
-	CSU_NSW = 0x80,
-	CSU_NSRW = 0x88,
-	CSU_NUR = 0x04,
-	CSU_NUW = 0x40,
-	CSU_NURW = 0x44,
-	CSU_SSR = 0x02,
-	CSU_SSW = 0x20,
-	CSU_SSRW = 0x22,
-	CSU_SUR = 0x01,
-	CSU_SUW = 0x10,
-	CSU_SURW = 0x11,
-	CSU_RW = 0xff,
-};
-
-enum csu_csln_idx {
-	CSU_CSLn_GPIO1 = 0,
-	CSU_CSLn_GPIO2 = 1,
-	CSU_CSLn_GPIO3 = 2,
-	CSU_CSLn_GPIO4 = 3,
-	CSU_CSLn_GPIO5 = 4,
-	CSU_CSLn_Reserved1 = 5,
-	CSU_CSLn_ANA_TSENSOR = 6,
-	CSU_CSLn_ANA_OSC = 7,
-	CSU_CSLn_WDOG1 = 8,
-	CSU_CSLn_WDOG2 = 9,
-	CSU_CSLn_WDOG3 = 10,
-	CSU_CSLn_Reserved2 = 11,
-	CSU_CSLn_SDMA2 = 12,
-	CSU_CSLn_GPT1 = 13,
-	CSU_CSLn_GPT2 = 14,
-	CSU_CSLn_GPT3 = 15,
-	CSU_CSLn_Reserved3 = 16,
-	CSU_CSLn_ROMCP = 17,
-	CSU_CSLn_LCDIF = 18,
-	CSU_CSLn_IOMUXC = 19,
-	CSU_CSLn_IOMUXC_GPR = 20,
-	CSU_CSLn_OCOTP_CTRL = 21,
-	CSU_CSLn_ANATOP_PLL = 22,
-	CSU_CSLn_SNVS_HP = 23,
-	CSU_CSLn_CCM = 24,
-	CSU_CSLn_SRC = 25,
-	CSU_CSLn_GPC = 26,
-	CSU_CSLn_SEMAPHORE1 = 27,
-	CSU_CSLn_SEMAPHORE2 = 28,
-	CSU_CSLn_RDC = 29,
-	CSU_CSLn_CSU = 30,
-	CSU_CSLn_Reserved4 = 31,
-	CSU_CSLn_MST0 = 32,
-	CSU_CSLn_MST1 = 33,
-	CSU_CSLn_MST2 = 34,
-	CSU_CSLn_MST3 = 35,
-	CSU_CSLn_HDMI_SEC = 36,
-	CSU_CSLn_Reserved5 = 37,
-	CSU_CSLn_PWM1 = 38,
-	CSU_CSLn_PWM2 = 39,
-	CSU_CSLn_PWM3 = 40,
-	CSU_CSLn_PWM4 = 41,
-	CSU_CSLn_SysCounter_RD = 42,
-	CSU_CSLn_SysCounter_CMP = 43,
-	CSU_CSLn_SysCounter_CTRL = 44,
-	CSU_CSLn_HDMI_CTRL = 45,
-	CSU_CSLn_GPT6 = 46,
-	CSU_CSLn_GPT5 = 47,
-	CSU_CSLn_GPT4 = 48,
-	CSU_CSLn_TZASC = 56,
-	CSU_CSLn_MTR = 59,
-	CSU_CSLn_PERFMON1 = 60,
-	CSU_CSLn_PERFMON2 = 61,
-	CSU_CSLn_PLATFORM_CTRL = 62,
-	CSU_CSLn_QoSC = 63,
-	CSU_CSLn_MIPI_PHY = 64,
-	CSU_CSLn_MIPI_DSI = 65,
-	CSU_CSLn_I2C1 = 66,
-	CSU_CSLn_I2C2 = 67,
-	CSU_CSLn_I2C3 = 68,
-	CSU_CSLn_I2C4 = 69,
-	CSU_CSLn_UART4 = 70,
-	CSU_CSLn_MIPI_CSI1 = 71,
-	CSU_CSLn_MIPI_CSI_PHY1 = 72,
-	CSU_CSLn_CSI1 = 73,
-	CSU_CSLn_MU_A = 74,
-	CSU_CSLn_MU_B = 75,
-	CSU_CSLn_SEMAPHORE_HS = 76,
-	CSU_CSLn_Internal1 = 77,
-	CSU_CSLn_SAI1 = 78,
-	CSU_CSLn_Reserved7 = 79,
-	CSU_CSLn_SAI6 = 80,
-	CSU_CSLn_SAI5 = 81,
-	CSU_CSLn_SAI4 = 82,
-	CSU_CSLn_Internal2 = 83,
-	CSU_CSLn_USDHC1 = 84,
-	CSU_CSLn_USDHC2 = 85,
-	CSU_CSLn_MIPI_CSI2 = 86,
-	CSU_CSLn_MIPI_CSI_PHY2 = 87,
-	CSU_CSLn_CSI2 = 88,
-	CSU_CSLn_Internal3 = 89,
-	CSU_CSLn_Reserved10 = 90,
-	CSU_CSLn_QSPI = 91,
-	CSU_CSLn_Reserved11 = 92,
-	CSU_CSLn_SDMA1 = 93,
-	CSU_CSLn_ENET1 = 94,
-	CSU_CSLn_Reserved12 = 95,
-	CSU_CSLn_Internal4 = 96,
-	CSU_CSLn_SPDIF1 = 97,
-	CSU_CSLn_ECSPI1 = 98,
-	CSU_CSLn_ECSPI2 = 99,
-	CSU_CSLn_ECSPI3 = 100,
-	CSU_CSLn_Reserved14 = 101,
-	CSU_CSLn_UART1 = 102,
-	CSU_CSLn_Internal5 = 103,
-	CSU_CSLn_UART3 = 104,
-	CSU_CSLn_UART2 = 105,
-	CSU_CSLn_SPDIF2 = 106,
-	CSU_CSLn_SAI2 = 107,
-	CSU_CSLn_SAI3 = 108,
-	CSU_CSLn_Reserved16 = 109,
-	CSU_CSLn_Internal6 = 110,
-	CSU_CSLn_SPBA1 = 111,
-	CSU_CSLn_MOD_EN3 = 112,
-	CSU_CSLn_MOD_EN0 = 113,
-	CSU_CSLn_CAAM = 114,
-	CSU_CSLn_DDRC_SEC = 115,
-	CSU_CSLn_GIC_EXSC = 116,
-	CSU_CSLn_USB_EXSC = 117,
-	CSU_CSLn_OCRAM_TZ = 118,
-	CSU_CSLn_OCRAM_S_TZ = 119,
-	CSU_CSLn_VPU_SEC = 120,
-	CSU_CSLn_DAP_EXSC = 121,
-	CSU_CSLn_ROMCP_SEC = 122,
-	CSU_CSLn_APBHDMA_SEC = 123,
-	CSU_CSLn_M4_SEC = 124,
-	CSU_CSLn_QSPI_SEC = 125,
-	CSU_CSLn_GPU_EXSC = 126,
-	CSU_CSLn_PCIE = 127,
-};
-
-enum csu_hp_idx {
-	CSU_HP_A53,
-	CSU_HP_M4,
-	CSU_HP_SDMA1,
-	CSU_HP_CSI,
-	CSU_HP_USB,
-	CSU_HP_PCIE,
-	CSU_HP_VPU,
-	CSU_HP_GPU,
-	CSU_HP_APBHDMA,
-	CSU_HP_ENET,
-	CSU_HP_USDHC1,
-	CSU_HP_USDHC2,
-	CSU_HP_DCSS,
-	CSU_HP_HUGO,
-	CSU_HP_DAP,
-	CSU_HP_SDMA2,
-	CSU_HP_CAAM,
-};
-
-enum csu_sa_idx {
-	CSU_SA_M4,
-	CSU_SA_SDMA1,
-	CSU_SA_CSI,
-	CSU_SA_USB,
-	CSU_SA_PCIE,
-	CSU_SA_VPU,
-	CSU_SA_GPU,
-	CSU_SA_APBHDMA,
-	CSU_SA_ENET,
-	CSU_SA_USDHC1,
-	CSU_SA_USDHC2,
-	CSU_SA_DCSS,
-	CSU_SA_HUGO,
-	CSU_SA_DAP,
-	CSU_SA_SDMA2,
-	CSU_SA_CAAM,
-};
-
-struct csu_slave_conf {
-	enum csu_csln_idx index;
-	uint16_t mode;
-	uint16_t lock;
-};
-
-struct csu_sa_conf {
-	enum csu_sa_idx index;
-	uint8_t enable;
-	uint8_t lock;
-};
-
-void csu_set_slave_index_mode(enum csu_csln_idx index,
-			uint16_t mode, uint8_t lock);
-void csu_get_slave_index_mode(enum csu_csln_idx index,
-			uint16_t *mode, uint8_t *lock);
-void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count);
-void csu_set_default_slaves_modes(void);
-void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable,
-			uint8_t set_control, uint8_t lock);
-void csu_set_sa_index_config(enum csu_sa_idx index, uint8_t enable,
-			uint8_t lock);
-void csu_get_sa_index_config(enum csu_sa_idx index, uint8_t *enable,
-			uint8_t *lock);
-void csu_set_sa_configs(struct csu_sa_conf *sa_configs,  uint32_t count);
-void csu_set_default_secure_configs(void);
-
-#if defined (CSU_RDC_TEST)
-void csu_test(void);
-#endif
-#endif /* __IMX_CSU_H__ */
diff --git a/plat/imx/imx8mq/include/imx_rdc.h b/plat/imx/imx8mq/include/imx_rdc.h
deleted file mode 100644
index 1b7179cc..00000000
--- a/plat/imx/imx8mq/include/imx_rdc.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __IMX_RDC_H__
-#define __IMX_RDC_H__
-
-/* Masters index */
-enum rdc_mda_idx {
-	RDC_MDA_A53 = 0,
-	RDC_MDA_M4 = 1,
-	RDC_MDA_PCIE_CTRL1 = 2,
-	RDC_MDA_PCIE_CTRL2 = 3,
-	RDC_MDA_VPU_DEC = 4,
-	RDC_MDA_LCDIF = 5,
-	RDC_MDA_CSI1 = 6,
-	RDC_MDA_CSI2 = 7,
-	RDC_MDA_Coresight = 8,
-	RDC_MDA_DAP = 9,
-	RDC_MDA_CAAM = 10,
-	RDC_MDA_SDMAp = 11,
-	RDC_MDA_SDMAb = 12,
-	RDC_MDA_APBHDMA = 13,
-	RDC_MDA_RAWNAND = 14,
-	RDC_MDA_uSDHC1 = 15,
-	RDC_MDA_uSDHC2 = 16,
-	RDC_MDA_DCSS = 17,
-	RDC_MDA_GPU = 18,
-	RDC_MDA_USB1 = 19,
-	RDC_MDA_USB2 = 20,
-	RDC_MDA_TESTPORT = 21,
-	RDC_MDA_ENET1_TX = 22,
-	RDC_MDA_ENET1_RX = 23,
-	RDC_MDA_SDMA2 = 24,
-	RDC_MDA_Reserved = 25,
-	RDC_MDA_SDMA1 = 26,
-};
-
-/* Peripherals index */
-enum rdc_pdap_idx {
-	RDC_PDAP_GPIO1 = 0,
-	RDC_PDAP_GPIO2 = 1,
-	RDC_PDAP_GPIO3 = 2,
-	RDC_PDAP_GPIO4 = 3,
-	RDC_PDAP_GPIO5 = 4,
-	RDC_PDAP_Reserved1 = 5,
-	RDC_PDAP_ANA_TSENSOR = 6,
-	RDC_PDAP_ANA_OSC = 7,
-	RDC_PDAP_WDOG1 = 8,
-	RDC_PDAP_WDOG2 = 9,
-	RDC_PDAP_WDOG3 = 10,
-	RDC_PDAP_Reserved2 = 11,
-	RDC_PDAP_SDMA2 = 12,
-	RDC_PDAP_GPT1 = 13,
-	RDC_PDAP_GPT2 = 14,
-	RDC_PDAP_GPT3 = 15,
-	RDC_PDAP_Reserved3 = 16,
-	RDC_PDAP_ROMCP = 17,
-	RDC_PDAP_LCDIF = 18,
-	RDC_PDAP_IOMUXC = 19,
-	RDC_PDAP_IOMUXC_GPR = 20,
-	RDC_PDAP_OCOTP_CTRL = 21,
-	RDC_PDAP_ANATOP_PLL = 22,
-	RDC_PDAP_SNVS_HP = 23,
-	RDC_PDAP_CCM = 24,
-	RDC_PDAP_SRC = 25,
-	RDC_PDAP_GPC = 26,
-	RDC_PDAP_SEMAPHORE1 = 27,
-	RDC_PDAP_SEMAPHORE2 = 28,
-	RDC_PDAP_RDC = 29,
-	RDC_PDAP_CSU = 30,
-	RDC_PDAP_Reserved4 = 31,
-	RDC_PDAP_MST0 = 32,
-	RDC_PDAP_MST1 = 33,
-	RDC_PDAP_MST2 = 34,
-	RDC_PDAP_MST3 = 35,
-	RDC_PDAP_HDMI_SEC = 36,
-	RDC_PDAP_Reserved5 = 37,
-	RDC_PDAP_PWM1 = 38,
-	RDC_PDAP_PWM2 = 39,
-	RDC_PDAP_PWM3 = 40,
-	RDC_PDAP_PWM4 = 41,
-	RDC_PDAP_SysCounter_RD = 42,
-	RDC_PDAP_SysCounter_CMP = 43,
-	RDC_PDAP_SysCounter_CTRL = 44,
-	RDC_PDAP_HDMI_CTRL = 45,
-	RDC_PDAP_GPT6 = 46,
-	RDC_PDAP_GPT5 = 47,
-	RDC_PDAP_GPT4 = 48,
-	RDC_PDAP_TZASC = 56,
-	RDC_PDAP_MTR = 59,
-	RDC_PDAP_PERFMON1 = 60,
-	RDC_PDAP_PERFMON2 = 61,
-	RDC_PDAP_PLATFORM_CTRL = 62,
-	RDC_PDAP_QoSC = 63,
-	RDC_PDAP_MIPI_PHY = 64,
-	RDC_PDAP_MIPI_DSI = 65,
-	RDC_PDAP_I2C1 = 66,
-	RDC_PDAP_I2C2 = 67,
-	RDC_PDAP_I2C3 = 68,
-	RDC_PDAP_I2C4 = 69,
-	RDC_PDAP_UART4 = 70,
-	RDC_PDAP_MIPI_CSI1 = 71,
-	RDC_PDAP_MIPI_CSI_PHY1 = 72,
-	RDC_PDAP_CSI1 = 73,
-	RDC_PDAP_MU_A = 74,
-	RDC_PDAP_MU_B = 75,
-	RDC_PDAP_SEMAPHORE_HS = 76,
-	RDC_PDAP_Reserved6 = 77,
-	RDC_PDAP_SAI1 = 78,
-	RDC_PDAP_Reserved7 = 79,
-	RDC_PDAP_SAI6 = 80,
-	RDC_PDAP_SAI5 = 81,
-	RDC_PDAP_SAI4 = 82,
-	RDC_PDAP_Reserved8 = 83,
-	RDC_PDAP_USDHC1 = 84,
-	RDC_PDAP_USDHC2 = 85,
-	RDC_PDAP_MIPI_CSI2 = 86,
-	RDC_PDAP_MIPI_CSI_PHY2 = 87,
-	RDC_PDAP_CSI2 = 88,
-	RDC_PDAP_Reserved9 = 89,
-	RDC_PDAP_Reserved10 = 90,
-	RDC_PDAP_QSPI = 91,
-	RDC_PDAP_Reserved11 = 92,
-	RDC_PDAP_SDMA1 = 93,
-	RDC_PDAP_ENET1 = 94,
-	RDC_PDAP_Reserved12 = 95,
-	RDC_PDAP_Reserved13 = 96,
-	RDC_PDAP_SPDIF1 = 97,
-	RDC_PDAP_ECSPI1 = 98,
-	RDC_PDAP_ECSPI2 = 99,
-	RDC_PDAP_ECSPI3 = 100,
-	RDC_PDAP_Reserved14 = 101,
-	RDC_PDAP_UART1 = 102,
-	RDC_PDAP_Reserved15 = 103,
-	RDC_PDAP_UART3 = 104,
-	RDC_PDAP_UART2 = 105,
-	RDC_PDAP_SPDIF2 = 106,
-	RDC_PDAP_SAI2 = 107,
-	RDC_PDAP_SAI3 = 108,
-	RDC_PDAP_Reserved16 = 109,
-	RDC_PDAP_Reserved17 = 110,
-	RDC_PDAP_SPBA1 = 111,
-	RDC_PDAP_CAAM = 114,
-	RDC_PDAP_DDRC_SEC = 115,
-	RDC_PDAP_GIC_EXSC = 116,
-	RDC_PDAP_USB_EXSC = 117,
-	RDC_PDAP_OCRAM_TZ = 118,
-	RDC_PDAP_OCRAM_S_TZ = 119,
-	RDC_PDAP_VPU_SEC = 120,
-	RDC_PDAP_DAP_EXSC = 121,
-	RDC_PDAP_ROMCP_SEC = 122,
-	RDC_PDAP_APBHDMA_SEC = 123,
-	RDC_PDAP_M4_SEC = 124,
-	RDC_PDAP_QSPI_SEC = 125,
-	RDC_PDAP_GPU_EXSC = 126,
-	RDC_PDAP_PCIE = 127,
-};
-
-/* RDC registers mapping */
-struct imx_rdc_regs {
-	uint32_t	vir;		/* Version information */
-	uint32_t	reserved1[8];
-	uint32_t	stat;		/* Status */
-	uint32_t	intctrl;	/* Interrupt and Control */
-	uint32_t	intstat;	/* Interrupt Status */
-	uint32_t	reserved2[116];
-	uint32_t	mda[27];		/* Master Domain Assignment */
-	uint32_t	reserved3[101];
-	uint32_t	pdap[118];		/* Peripheral Domain Access Permissions */
-	uint32_t	reserved4[138];
-	struct {
-		uint32_t mrsa;		/* Memory Region Start Address */
-		uint32_t mrea;		/* Memory Region End Address */
-		uint32_t mrc;		/* Memory Region Control */
-		uint32_t mrvs;		/* Memory Region Violation Status */
-	} mem_region[52];
-};
-
-struct rdc_pdap_conf {
-	enum rdc_pdap_idx	index;	/* Peripheral index */
-	uint8_t	domains;	/* Assigned domains */
-	uint8_t	lock;	/* Lock */
-};
-
-struct rdc_mda_conf {
-	enum rdc_mda_idx	index;	/* Master index */
-	uint8_t	domain;	/* Assigned domain */
-	uint8_t	lock;	/* Lock */
-};
-
-#define RDC_MDA_DID_SHIFT	0
-#define RDC_MDA_DID_MASK	(0x3 << RDC_MDA_DID_SHIFT)
-#define RDC_MDA_LCK_SHIFT	31
-#define RDC_MDA_LCK_MASK	(0x1 << RDC_MDA_LCK_SHIFT)
-
-#define RDC_PDAP_DW_SHIFT(domain)	((domain) << 1)
-#define RDC_PDAP_DR_SHIFT(domain)	(1 + RDC_PDAP_DW_SHIFT(domain))
-#define RDC_PDAP_DW_MASK(domain)	(1 << RDC_PDAP_DW_SHIFT(domain))
-#define RDC_PDAP_DR_MASK(domain)	(1 << RDC_PDAP_DR_SHIFT(domain))
-#define RDC_PDAP_DRW_MASK(domain)	(RDC_PDAP_DW_MASK(domain) | \
-					 RDC_PDAP_DR_MASK(domain))
-
-#define RDC_PDAP_SREQ_SHIFT	30
-#define RDC_PDAP_SREQ_MASK	(0x1 << RDC_PDAP_SREQ_SHIFT)
-#define RDC_PDAP_LCK_SHIFT	31
-#define RDC_PDAP_LCK_MASK	(0x1 << RDC_PDAP_LCK_SHIFT)
-
-int imx_rdc_get_pdap(struct rdc_pdap_conf *p);
-int imx_rdc_set_pdap(struct rdc_pdap_conf *p);
-int imx_rdc_set_peripherals(struct rdc_pdap_conf *peripheral_list,
-				uint32_t count);
-void imx_rdc_set_peripherals_default(void);
-int imx_rdc_get_mda(struct rdc_mda_conf *p);
-int imx_rdc_set_mda(struct rdc_mda_conf *p);
-int imx_rdc_set_masters(struct rdc_mda_conf *masters_list, uint32_t count);
-void imx_rdc_set_masters_default(void);
-
-#if defined (CSU_RDC_TEST)
-void rdc_test(void);
-#endif
-#endif	/* __IMX_RDC_H__*/
diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk
index 4065e452..8cddf99a 100644
--- a/plat/imx/imx8mq/platform.mk
+++ b/plat/imx/imx8mq/platform.mk
@@ -21,8 +21,8 @@ BL31_SOURCES		+=	plat/imx/common/imx8_helpers.S		\
 				plat/imx/common/imx8m/hab.c		\
 				plat/imx/imx8mq/gpc.c			\
 				plat/imx/imx8mq/imx8mq_psci.c		\
-				plat/imx/imx8mq/imx_csu.c		\
-				plat/imx/imx8mq/imx_rdc.c		\
+				plat/imx/common/imx8m/imx_csu.c		\
+				plat/imx/common/imx8m/imx_rdc.c		\
 				plat/imx/common/imx8_topology.c		\
 				plat/common/plat_psci_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c	\