diff options
| author | Peng Fan <peng.fan@nxp.com> | 2017-11-01 17:59:35 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:40 +0300 |
| commit | 7280cd36cc7ca6e3a3703ee3c03c9c582d937205 (patch) | |
| tree | fe08ccafee7ef1400af7bb44fe1936c1b21466ed /plat/imx/imx8mq | |
| parent | bb1935d40c23e381b2ff9a7ed49935ca4a404376 (diff) | |
imx8mq: add src sip to handle m4
Add src sip to handle M4 boot and status check
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/platform.mk | 1 | ||||
| -rw-r--r-- | plat/imx/imx8mq/src.c | 45 |
2 files changed, 46 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk index 50196d11..16114123 100644 --- a/plat/imx/imx8mq/platform.mk +++ b/plat/imx/imx8mq/platform.mk @@ -11,6 +11,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/common/mxcuart_console.S \ plat/imx/common/sip_svc.c \ plat/imx/imx8mq/imx8m_bl31_setup.c \ + plat/imx/imx8mq/src.c \ plat/imx/imx8mq/gpc.c \ plat/imx/imx8mq/ddrc.c \ plat/imx/imx8mq/imx8m_psci.c \ diff --git a/plat/imx/imx8mq/src.c b/plat/imx/imx8mq/src.c new file mode 100644 index 00000000..4fa0e2c3 --- /dev/null +++ b/plat/imx/imx8mq/src.c @@ -0,0 +1,45 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <debug.h> +#include <stdlib.h> +#include <stdint.h> +#include <stdbool.h> +#include <smcc_helpers.h> +#include <std_svc.h> +#include <types.h> +#include <mmio.h> +#include <platform_def.h> +#include <fsl_sip.h> +#include <soc.h> + +#define M4RCR (0xC) +#define SRC_SCR_M4_ENABLE_OFFSET 3 +#define SRC_SCR_M4_ENABLE_MASK (1 << 3) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 0) +int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, + u_register_t x3) +{ + uint32_t val; + + switch(x1) { + case FSL_SIP_SRC_M4_START: + val = mmio_read_32(IMX_SRC_BASE + M4RCR); + val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK; + val |= SRC_SCR_M4_ENABLE_MASK; + mmio_write_32(IMX_SRC_BASE + M4RCR, val); + break; + case FSL_SIP_SRC_M4_STARTED: + val = mmio_read_32(IMX_SRC_BASE + M4RCR); + return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK); + default: + return SMC_UNK; + + }; + + return 0; +} |