diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-01-24 14:14:21 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:02 +0300 |
| commit | 5b1d3771ebb1e4489e3b413dbdac82249d8d60b1 (patch) | |
| tree | e202c00073746b35f6d49a0d415c1fc7d0afa647 /plat/imx/imx8mq | |
| parent | 5c97d1df7ce9756d4a30b0c5b85dc1d77ae44a2a (diff) | |
plat: imx8mq: Improve the DDR DVFS flow on imx8mq
Flush the L1 and L2 cache before DDR frequency change to
make sure that no DDR memory access caused by cache activity.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
| -rw-r--r-- | plat/imx/imx8mq/ddrc.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/plat/imx/imx8mq/ddrc.c b/plat/imx/imx8mq/ddrc.c index 40dec4c5..ec8cc07d 100644 --- a/plat/imx/imx8mq/ddrc.c +++ b/plat/imx/imx8mq/ddrc.c @@ -2964,17 +2964,19 @@ int lpddr4_dvfs_handler(uint32_t smc_fid, } } - mmio_write_32(0x30340004, mmio_read_32(0x30340004) | (1 << 12)); - /* make sure all the core in WFE */ online_cores &= ~(0x1 << (cpu_id * 8)); while (1) { + mmio_write_32(0x30340004, mmio_read_32(0x30340004) | (1 << 12)); if (online_cores == wfe_done) break; } mmio_write_32(0x30340004, mmio_read_32(0x30340004) & ~(1 << 12)); + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + lpddr4_dvfs_hwffc(init_vrcg, init_fsp, target_freq, discamdrain); init_fsp = (~init_fsp) & 0x1; wait_ddrc_hwffc_done = false; |