plat: imx8mm: add basic imx8mm support

i.MX8MM is a new soc of the i.MX8M family, this patch
add the basic support for i.MX8MM. further code optimization
needed. WAIT mode support is currently disabled, will be enabled
later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

1 files changed, 60 insertions, 0 deletions

diff --git a/plat/imx/imx8mm/misc.c b/plat/imx/imx8mm/misc.c
new file mode 100644
index 00000000..9c2c0ace
--- /dev/null
+++ b/plat/imx/imx8mm/misc.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <smcc_helpers.h>
+#include <std_svc.h>
+#include <types.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <fsl_sip.h>
+#include <soc.h>
+
+#define M4RCR (0xC)
+#define SRC_SCR_M4_ENABLE_OFFSET		3
+#define SRC_SCR_M4_ENABLE_MASK			(1 << 3)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET		0
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK		(1 << 0)
+
+#define DIGPROG		0x800
+
+int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	uint32_t val;
+
+	switch(x1) {
+	case FSL_SIP_SRC_M4_START:
+		val = mmio_read_32(IMX_SRC_BASE + M4RCR);
+		val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK;
+		val |= SRC_SCR_M4_ENABLE_MASK;
+		mmio_write_32(IMX_SRC_BASE + M4RCR, val);
+		break;
+	case FSL_SIP_SRC_M4_STARTED:
+		val = mmio_read_32(IMX_SRC_BASE + M4RCR);
+		return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK);
+	default:
+		return SMC_UNK;
+
+	};
+
+	return 0;
+}
+
+int imx_soc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	return mmio_read_32(IMX_ANAMIX_BASE + DIGPROG);
+}
+
+int imx_noc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+		    u_register_t x3)
+{
+	return 0;
+}