diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-07-11 16:23:08 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2018-07-20 18:03:57 +0800 |
| commit | f0893b1f52303ba5604480db71efe605161666eb (patch) | |
| tree | 34c59fe4b828bc80d2bd6b7ea4f99eeac6d159ef /plat/imx/imx8mm/imx8mm_bl31_setup.c | |
| parent | 3278759d99e76a51193479ef2e38ab2353b875c0 (diff) | |
plat: imx: refact the dram retention flow on imx8mm
All the DRAM timing related config is saved by SPL in OCRAM_S,
so no need to do save for these configs in ATF anymore.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8mm/imx8mm_bl31_setup.c')
| -rw-r--r-- | plat/imx/imx8mm/imx8mm_bl31_setup.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c index 22e50bf9..43309d31 100644 --- a/plat/imx/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c @@ -267,6 +267,8 @@ void bl31_plat_arch_setup(void) /* Map DDRC/PHY/PERF */ mmap_add_region(0x3c000000, 0x3c000000, 0x4000000, MT_DEVICE | MT_RW); + mmap_add_region(0x180000, 0x180000, 0x8000, MT_MEMORY | MT_RW); + #if USE_COHERENT_MEM mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE, @@ -285,7 +287,7 @@ void bl31_platform_setup(void) mmio_write_32(0x30360124, 0x1); /* init the dram info */ - dram_info_init(); + dram_info_init(SAVED_DRAM_TIMING_BASE); /* init the GICv3 cpu and distributor interface */ plat_gic_driver_init(); |