diff options
| author | Bai Ping <ping.bai@nxp.com> | 2018-06-05 13:07:38 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:33:03 +0300 |
| commit | 7f83fd077208220c57a389871abb987d371ca50c (patch) | |
| tree | f6ca6db625d23aeb8b1621821446752a34e2e07b /plat/imx/imx8mm/gpc.c | |
| parent | 21fa6238d98517739e9e65cd6431a1e5a0880a52 (diff) | |
MLK-18502-02 plat: imx8mm: keep L2 cache memory power in WAIT mode
When system enter deepest cpuilde(WAIT mode), the L2 cache memory
can be on for retention to increase the system performance. So
the WAIT mode with cluster power down should be defined as
rentention power state in PSCI. changing the WAIT_OFF_STATE to
WAIT_RET_STATE to make sure the l2 cache memory is not
clean & invalidate.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8mm/gpc.c')
| -rw-r--r-- | plat/imx/imx8mm/gpc.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c index bfa0c5c1..3a1242dd 100644 --- a/plat/imx/imx8mm/gpc.c +++ b/plat/imx/imx8mm/gpc.c @@ -159,7 +159,7 @@ #define COREx_PGC_PCR(core_id) (0x800 + core_id * 0x40) #define COREx_WFI_PDN(core_id) (1 << (core_id < 2 ? core_id * 2 : (core_id - 2) * 2 + 16)) #define COREx_IRQ_WUP(core_id) (core_id < 2 ? (1 << (core_id * 2 + 8)) : (1 << (core_id * 2 + 20))); -#define LPM_MODE(local_state) (local_state == PLAT_WAIT_OFF_STATE ? A53_LPM_WAIT : A53_LPM_STOP) +#define LPM_MODE(local_state) (local_state == PLAT_WAIT_RET_STATE ? A53_LPM_WAIT : A53_LPM_STOP) #define A53_CORE_WUP_SRC(core_id) (1 << (core_id < 2 ? 28 + core_id : 22 + core_id - 2)) #define IMR_MASK_ALL 0xffffffff @@ -380,7 +380,7 @@ void imx_set_cluster_powerdown(int last_core, uint8_t power_state) { uint32_t val; - if (is_local_state_off(power_state)) { + if (!is_local_state_run(power_state)) { /* config A53 cluster LPM mode */ val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_BSC); @@ -396,7 +396,13 @@ void imx_set_cluster_powerdown(int last_core, uint8_t power_state) /* enable PLAT/SCU power down */ val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); val &= ~EN_L2_WFI_PDN; - val |= (L2PGE | EN_PLAT_PDN); + + /* L2 cache memory is on in WAIT mode */ + if (is_local_state_off(power_state)) + val |= (L2PGE | EN_PLAT_PDN); + else + val |= EN_PLAT_PDN; + mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); /* config SLOT for PLAT power up/down */ |