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authorJacky Bai <ping.bai@nxp.com>2020-03-31 16:42:50 +0800
committerJacky Bai <ping.bai@nxp.com>2020-03-31 17:47:27 +0800
commit25ce865155010545fa70256bbc2089b464c79f87 (patch)
tree6a834cdefa9aca5f2cb24a42523cde2b81e4d207 /plat/imx/imx8m/imx8mp/include/platform_def.h
parent2704540b4a7952d73e702a3e079c13c6af5ef03a (diff)
plat: imx8m: Fix the m4 enabled check for imx8m
On i.MX8MN & i.MX8MP, the M core enabled check should relay on the IOMUX GPR CPU_WAIT bit, when this bit is cleared, it means M core is active & running, so refine the m4 enabled check method. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8m/imx8mp/include/platform_def.h')
-rw-r--r--plat/imx/imx8m/imx8mp/include/platform_def.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index bcd45343..ecbe0c5f 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -129,7 +129,7 @@
#define IOMUXC_GPR22 U(0x58)
#define GPR_CM7_CPUWAIT BIT(0)
#define IMX_M4_STATUS (IMX_IOMUX_GPR_BASE + IOMUXC_GPR22)
-#define IMX_M4_ENABLED GPR_CM7_CPUWAIT
+#define IMX_M4_ENABLED_MASK GPR_CM7_CPUWAIT
#define ANAMIX_MISC_CTL U(0x124)