diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-01-14 17:46:23 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-02-09 20:58:49 +0800 |
| commit | 55194d21a18003224451b75c73838ef3a410c7cb (patch) | |
| tree | d3666b2844c7f1f02f114a09b3666ba282b50f5a /plat/imx/imx8m/imx8mm | |
| parent | 563016d45a91a9f1501aa43b22e7db9705605346 (diff) | |
plat: imx8m: Add the src handler for m4/m7 core boot support
Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8m/imx8mm')
| -rw-r--r-- | plat/imx/imx8m/imx8mm/gpc.c | 23 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 4 |
2 files changed, 27 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index 3051ce3a..a1bbe35b 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -394,3 +394,26 @@ void imx_gpc_init(void) mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1); mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1); } + +int imx_src_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, + u_register_t x3) +{ + uint32_t val; + + switch(x1) { + case IMX_SIP_SRC_M4_START: + val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR); + val &= ~SRC_SCR_M4C_NON_SCLR_RST_MASK; + val |= SRC_SCR_M4_ENABLE_MASK; + mmio_write_32(IMX_SRC_BASE + SRC_M4RCR, val); + break; + case IMX_SIP_SRC_M4_STARTED: + val = mmio_read_32(IMX_SRC_BASE + SRC_M4RCR); + return !(val & SRC_SCR_M4C_NON_SCLR_RST_MASK); + default: + return SMC_UNK; + + }; + + return 0; +} diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index dbe579a7..5eedaa02 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -111,10 +111,14 @@ #define SRC_A53RCR0 U(0x4) #define SRC_A53RCR1 U(0x8) +#define SRC_M4RCR U(0xc) #define SRC_OTG1PHY_SCR U(0x20) #define SRC_OTG2PHY_SCR U(0x24) #define SRC_GPR1_OFFSET U(0x74) +#define SRC_SCR_M4_ENABLE_MASK BIT(3) +#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) + #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) #define SNVS_LPCR_DP_EN BIT(5) |