diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-01-20 13:56:56 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-02-09 20:58:49 +0800 |
| commit | 2a045c8600f2bcab3a7bd7c36c64db49638ed1a9 (patch) | |
| tree | fc3d5d887db84d349af63b3973441d077f6773d3 /plat/imx/imx8m/imx8mm | |
| parent | 9dec5b6f55f236304f40f2181e3784c01708a97a (diff) | |
plat: imx8m: Add the M4 low power audio support on imx8m
Add the M core low power audio support on i.MX8M.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8m/imx8mm')
| -rw-r--r-- | plat/imx/imx8m/imx8mm/gpc.c | 3 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c | 2 | ||||
| -rw-r--r-- | plat/imx/imx8m/imx8mm/include/platform_def.h | 2 |
3 files changed, 6 insertions, 1 deletions
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index afd39051..75e103d7 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -443,8 +443,9 @@ void imx_gpc_init(void) /* clear DSM by default */ val = mmio_read_32(IMX_GPC_BASE + SLPCR); val &= ~SLPCR_EN_DSM; - /* enable the fast wakeup wait mode */ + /* enable the fast wakeup wait/stop mode */ val |= SLPCR_A53_FASTWUP_WAIT_MODE; + val |= SLPCR_A53_FASTWUP_STOP_MODE; /* clear the RBC */ val &= ~(0x3f << SLPCR_RBC_COUNT_SHIFT); /* set the STBY_COUNT to 0x5, (128 * 30)us */ diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c index 1e7b32fa..1f0e21cb 100644 --- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c +++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c @@ -56,6 +56,8 @@ static const struct imx_rdc_cfg rdc[] = { RDC_MDAn(0x1, DID1), /* peripherals domain permission */ + RDC_PDAPn(70, D1R | D1W), + RDC_PDAPn(105, D0R | D0W), /* memory region */ diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h index 5eedaa02..2d30f680 100644 --- a/plat/imx/imx8m/imx8mm/include/platform_def.h +++ b/plat/imx/imx8m/imx8mm/include/platform_def.h @@ -118,6 +118,8 @@ #define SRC_SCR_M4_ENABLE_MASK BIT(3) #define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0) +#define IMX_M4_STATUS (IMX_SRC_BASE + SRC_M4RCR) +#define IMX_M4_ENABLED SRC_SCR_M4C_NON_SCLR_RST_MASK #define SNVS_LPCR U(0x38) #define SNVS_LPCR_SRTC_ENV BIT(0) |