diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-03-23 15:54:01 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-03-27 20:52:50 +0800 |
| commit | de9f6ef06affd646ec789fb832913db058321186 (patch) | |
| tree | a96bbc3bcb613a0c8acfe02edd929f7091b90eef /plat/imx/imx8m/imx8mm/gpc.c | |
| parent | ac5f80377ff574d721a9f966cecd0f1f63c22e94 (diff) | |
plat: imx8m: move the gpc reg & macro to a separate header file
move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8m/imx8mm/gpc.c')
| -rw-r--r-- | plat/imx/imx8m/imx8mm/gpc.c | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/plat/imx/imx8m/imx8mm/gpc.c b/plat/imx/imx8m/imx8mm/gpc.c index b18071a0..33a83613 100644 --- a/plat/imx/imx8m/imx8mm/gpc.c +++ b/plat/imx/imx8m/imx8mm/gpc.c @@ -21,47 +21,6 @@ #include <imx_sip_svc.h> #include <plat_imx8.h> -#define MIPI_PWR_REQ BIT(0) -#define PCIE_PWR_REQ BIT(1) -#define OTG1_PWR_REQ BIT(2) -#define OTG2_PWR_REQ BIT(3) -#define HSIOMIX_PWR_REQ BIT(4) -#define GPU2D_PWR_REQ BIT(6) -#define GPUMIX_PWR_REQ BIT(7) -#define VPUMIX_PWR_REQ BIT(8) -#define GPU3D_PWR_REQ BIT(9) -#define DISPMIX_PWR_REQ BIT(10) -#define VPU_G1_PWR_REQ BIT(11) -#define VPU_G2_PWR_REQ BIT(12) -#define VPU_H1_PWR_REQ BIT(13) - -#define HSIOMIX_ADB400_SYNC (0x3 << 5) -#define DISPMIX_ADB400_SYNC BIT(7) -#define VPUMIX_ADB400_SYNC BIT(8) -#define GPU3D_ADB400_SYNC BIT(9) -#define GPU2D_ADB400_SYNC BIT(10) -#define GPUMIX_ADB400_SYNC BIT(11) -#define HSIOMIX_ADB400_ACK (0x3 << 23) -#define DISPMIX_ADB400_ACK BIT(25) -#define VPUMIX_ADB400_ACK BIT(26) -#define GPU3D_ADB400_ACK BIT(27) -#define GPU2D_ADB400_ACK BIT(28) -#define GPUMIX_ADB400_ACK BIT(29) - -#define MIPI_PGC 0xc00 -#define PCIE_PGC 0xc40 -#define OTG1_PGC 0xc80 -#define OTG2_PGC 0xcc0 -#define HSIOMIX_PGC 0xd00 -#define GPU2D_PGC 0xd80 -#define GPUMIX_PGC 0xdc0 -#define VPUMIX_PGC 0xe00 -#define GPU3D_PGC 0xe40 -#define DISPMIX_PGC 0xe80 -#define VPU_G1_PGC 0xec0 -#define VPU_G2_PGC 0xf00 -#define VPU_H1_PGC 0xf40 - #define CCGR(x) (0x4000 + (x) * 16) enum pu_domain_id { |