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author | Jacky Bai <ping.bai@nxp.com> | 2021-03-16 16:42:54 +0800 |
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committer | Jacky Bai <ping.bai@nxp.com> | 2021-03-26 14:45:24 +0800 |
commit | 768e16f784bd7462d7df684e24deb0b777bdfc28 (patch) | |
tree | 02ee828fa6bd797f2656ed02cf9c4cc0443ac392 /plat/imx/imx8m/imx8m_csu.c | |
parent | ed66400156db65fca3f69aae2536282555b63798 (diff) |
MLK-25345 plat: imx8m: Add ddr4 dvfs sw workaround for ERR050712
APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring
When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:
1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2)
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5)
Diffstat (limited to 'plat/imx/imx8m/imx8m_csu.c')
0 files changed, 0 insertions, 0 deletions