plat: imx8mq: Add workaround code for ERR11171 on imx8mq

This new workaround takes advantage of the per core IMR registers in GPC in
order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
(which now remains always set), so it can only wake up one core at the time.
Also, this entire workaround has now been moved here in TF-A, allowing the
kernel side to be minimal.

Another advantage this workaround brings is the removal of the 50us delay
(which was necessary before in gic_raise_softirq in kernel) by allowing the
core that is waking up to mask his own IRQ0 in the suspend finish callback.

One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
masking/unmasking the IMR1 1st bit for each independent core, we need to use
the imx_gpc_core_wake to wake up the cores.

Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
(gic_raise_softirq), since the new cpuidle workaround does not need it in order
to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
in order to delay the affinity info OFF for the dying core. This is something
that needs further investigation.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index 3233a7c8..fa058cc8 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -179,6 +179,7 @@ static unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id)
 	return mmio_read_32(base + GICD_ISENABLER + (n << 2));
 }
 
+#pragma weak imx_set_sys_wakeup
 /*
  * gic's clock will be gated in system suspend, so gic has no ability to
  * to wakeup the system, we need to config the imr based on the irq
@@ -293,6 +294,7 @@ void imx_anamix_override(bool enter)
 	}
 }
 
+#pragma weak imx_gpc_handler
 int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3)
 {
 	switch(x1) {