diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-05-08 17:37:24 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-05-09 16:04:39 +0800 |
| commit | fc2a8af0d9aa43097869ce62e0aa54872afa286e (patch) | |
| tree | 9d8e35cd566675841a7df416f2c345376024eb26 /plat/imx/imx8m/ddr/dram_retention.c | |
| parent | a9341549ea984f3b1414df15b01835bb5fa98675 (diff) | |
MLK-23821-04 plat: imx8m: Fix the rank to rank issue
update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 8cd4fa6dfff74b190294141bdc22634a7cb40a30)
Diffstat (limited to 'plat/imx/imx8m/ddr/dram_retention.c')
| -rw-r--r-- | plat/imx/imx8m/ddr/dram_retention.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c index b46d4410..6a19f0e7 100644 --- a/plat/imx/imx8m/ddr/dram_retention.c +++ b/plat/imx/imx8m/ddr/dram_retention.c @@ -19,6 +19,32 @@ #define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) #define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n)) +static void rank_setting_update(void) +{ + uint32_t i, offset; + uint32_t pstate_num = dram_info.num_fsp; + + for (i = 0; i < pstate_num; i++) { + offset = i ? (i + 1) * 0x1000 : 0; + if (dram_info.dram_type == DDRC_LPDDR4) { + mmio_write_32(DDRC_DRAMTMG2(0) + offset, + dram_info.rank_setting[i][0]); + } else { + mmio_write_32(DDRC_DRAMTMG2(0) + offset, + dram_info.rank_setting[i][0]); + mmio_write_32(DDRC_DRAMTMG9(0) + offset, + dram_info.rank_setting[i][1]); + } +#if !defined(PLAT_imx8mq) + mmio_write_32(DDRC_RANKCTL(0) + offset, + dram_info.rank_setting[i][2]); +#endif + } +#if defined(PLAT_imx8mq) + mmio_write_32(DDRC_RANKCTL(0), dram_info.rank_setting[0][2]); +#endif +} + void dram_enter_retention(void) { /* Wait DBGCAM to be empty */ @@ -132,6 +158,9 @@ void dram_exit_retention(void) /* dram phy re-init */ dram_phy_init(dram_info.timing_info); + /* workaround for rank-to-rank issue */ + rank_setting_update(); + /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ dwc_ddrphy_apb_wr(0xd0000, 0x0); while (dwc_ddrphy_apb_rd(0x20097)) |