diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-04-22 21:26:13 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-05-09 15:25:12 +0800 |
| commit | 57bf8a00a74f12671cb38863bbc3606b3834f195 (patch) | |
| tree | 305be17dd9f3523b29db35e04e3eb69054413cb3 /plat/imx/imx8m/ddr/dram.c | |
| parent | bc9bc03f38fecbf5a2e4d938ed6f45fb3ec0b574 (diff) | |
MLK-23821-02 plat: imx8m: update the ddr4 dvfs flow to include ddr3l support
the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Diffstat (limited to 'plat/imx/imx8m/ddr/dram.c')
| -rw-r--r-- | plat/imx/imx8m/ddr/dram.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c index 49385909..b886b931 100644 --- a/plat/imx/imx8m/ddr/dram.c +++ b/plat/imx/imx8m/ddr/dram.c @@ -189,6 +189,17 @@ void dram_info_init(unsigned long dram_timing_base) rc = register_interrupt_type_handler(INTR_TYPE_EL3, waiting_dvfs, flags); if (rc) panic(); + + if (dram_info.dram_type == DDRC_LPDDR4 && current_fsp != 0x0) { + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + lpddr4_swffc(&dram_info, dev_fsp, 0x0); + dev_fsp = (~dev_fsp) & 0x1; + } else if (current_fsp != 0x0) { + /* flush the L1/L2 cache */ + dcsw_op_all(DCCSW); + ddr4_swffc(&dram_info, 0x0); + } } @@ -272,7 +283,7 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle, if (dram_info.dram_type == DDRC_LPDDR4) { lpddr4_swffc(&dram_info, dev_fsp, fsp_index); dev_fsp = (~dev_fsp) & 0x1; - } else if (dram_info.dram_type == DDRC_DDR4) { + } else { ddr4_swffc(&dram_info, fsp_index); } |