diff options
| author | Jacky Bai <ping.bai@nxp.com> | 2020-05-08 17:37:24 +0800 |
|---|---|---|
| committer | Jacky Bai <ping.bai@nxp.com> | 2020-05-09 16:04:39 +0800 |
| commit | fc2a8af0d9aa43097869ce62e0aa54872afa286e (patch) | |
| tree | 9d8e35cd566675841a7df416f2c345376024eb26 /plat/imx/imx8m/ddr/dram.c | |
| parent | a9341549ea984f3b1414df15b01835bb5fa98675 (diff) | |
MLK-23821-04 plat: imx8m: Fix the rank to rank issue
update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 8cd4fa6dfff74b190294141bdc22634a7cb40a30)
Diffstat (limited to 'plat/imx/imx8m/ddr/dram.c')
| -rw-r--r-- | plat/imx/imx8m/ddr/dram.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c index b886b931..b206c716 100644 --- a/plat/imx/imx8m/ddr/dram.c +++ b/plat/imx/imx8m/ddr/dram.c @@ -71,6 +71,27 @@ static void get_mr_values(uint32_t (*mr_value)[8]) } } +static void save_rank_setting(void) +{ + uint32_t i, offset; + uint32_t pstate_num = dram_info.num_fsp; + + for(i = 0; i < pstate_num; i++) { + offset = i ? (i + 1) * 0x1000 : 0; + if (dram_info.dram_type == DDRC_LPDDR4) { + dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset); + } else { + dram_info.rank_setting[i][0] = mmio_read_32(DDRC_DRAMTMG2(0) + offset); + dram_info.rank_setting[i][1] = mmio_read_32(DDRC_DRAMTMG9(0) + offset); + } +#if !defined(PLAT_imx8mq) + dram_info.rank_setting[i][2] = mmio_read_32(DDRC_RANKCTL(0) + offset); +#endif + } +#if defined(PLAT_imx8mq) + dram_info.rank_setting[0][2] = mmio_read_32(DDRC_RANKCTL(0)); +#endif +} /* Restore the ddrc configs */ void dram_umctl2_init(struct dram_timing_info *timing) { @@ -178,6 +199,9 @@ void dram_info_init(unsigned long dram_timing_base) break; dram_info.num_fsp = i; + /* save the DRAMTMG2/9 for rank to rank workaround */ + save_rank_setting(); + /* check if has bypass mode support */ if (dram_info.timing_info->fsp_table[i-1] < 666) dram_info.bypass_mode = true; |