diff options
| author | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2018-11-29 15:59:14 +0000 |
|---|---|---|
| committer | Bryan O'Donoghue <bryan.odonoghue@linaro.org> | 2019-01-18 14:24:09 +0000 |
| commit | e483639ad2fe0f3f9425b218bf6c37b9fbafc78f (patch) | |
| tree | 426b3449d1fa9b39e56730718b53a9eff8b28462 /plat/imx/imx7 | |
| parent | c2f31c99fef7fe613f6b2f1db012c95c32f1ca08 (diff) | |
warp7: Define DTB overlay address in memory map
This patch defines the expected DTB overlay address in the memory map for
this platform. Its important that all points in the boot process agree on
this memory map even if not all elements utilize it.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Diffstat (limited to 'plat/imx/imx7')
| -rw-r--r-- | plat/imx/imx7/warp7/include/platform_def.h | 8 | ||||
| -rw-r--r-- | plat/imx/imx7/warp7/warp7_bl2_el3_setup.c | 13 |
2 files changed, 15 insertions, 6 deletions
diff --git a/plat/imx/imx7/warp7/include/platform_def.h b/plat/imx/imx7/warp7/include/platform_def.h index a931c806..d58382f3 100644 --- a/plat/imx/imx7/warp7/include/platform_def.h +++ b/plat/imx/imx7/warp7/include/platform_def.h @@ -106,6 +106,12 @@ #define WARP7_DTB_BASE (DRAM_BASE + 0x03000000) #define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE) +/* Define the absolute location of DTB Overlay 0x83100000 - 0x83101000 */ +#define WARP7_DTB_OVERLAY_SIZE 0x00001000 +#define WARP7_DTB_OVERLAY_BASE WARP7_DTB_LIMIT +#define WARP7_DTB_OVERLAY_LIMIT (WARP7_DTB_OVERLAY_BASE + \ + WARP7_DTB_OVERLAY_SIZE) + /* * BL2 specific defines. * @@ -142,6 +148,8 @@ * | DDR | BL33/U-BOOT * 0x87800000 +-----------------+ * | DDR | Unallocated + * 0x83101000 +-----------------+ + * | DDR | DTB Overlay * 0x83100000 +-----------------+ * | DDR | DTB * 0x83000000 +-----------------+ diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c index 032ed7b1..08baf199 100644 --- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c +++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c @@ -290,12 +290,13 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, imx_wdog_init(); /* Print out the expected memory map */ - VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); - VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); - VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); - VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); - VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); - VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); + VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT); + VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT); + VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT); + VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT); + VERBOSE("\tDTB-OVERLAY 0x%08x-0x%08x\n", WARP7_DTB_OVERLAY_BASE, WARP7_DTB_OVERLAY_LIMIT); + VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT); + VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT); } /* |