diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-10-31 11:17:48 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:40 +0300 |
| commit | 031cbe458830538c5e265c8c0eec290100236281 (patch) | |
| tree | 375b186c8393cdf5c166c597e1e3472e3ac79579 /plat/imx/common/sip_svc.c | |
| parent | 68c2cdd8cf00624e70449101169b49c266ad2703 (diff) | |
plat: imx8mq add ddr frequency support on imx8mq
When changing the DDR frequency, the DDRC will block
AXI access, so the code for changing the frequency need
to be run on OCRAM not make sure no DDR access at this stage.
the DDR frequency change request is from EL1 linux kernel side,
we use the SiP service call to trap the DDR frequency change operation
from linux kernel to ATF.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/common/sip_svc.c')
| -rw-r--r-- | plat/imx/common/sip_svc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/plat/imx/common/sip_svc.c b/plat/imx/common/sip_svc.c index 84a8e976..a45a0a35 100644 --- a/plat/imx/common/sip_svc.c +++ b/plat/imx/common/sip_svc.c @@ -43,6 +43,7 @@ extern int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, extern int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); extern int imx_srtc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3, u_register_t x4); +extern int lpddr4_dvfs_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); /* Setup i.MX platform specific services Services */ static int32_t plat_svc_setup(void) @@ -112,6 +113,9 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid, case FSL_SIP_GPC: SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); break; + case FSL_SIP_DDR_DVFS: + SMC_RET1(handle, lpddr4_dvfs_handler(smc_fid, x1, x2, x3)); + break; #endif #if (defined(PLAT_IMX8QM) || defined(PLAT_IMX8QXP)) case FSL_SIP_CPUFREQ: |