i.mx8mq: Add basic support for i.mx8mq

Add basic support for i.MX8MQ.
1. SMP support is ok.
2. basic suspend/resume support is ok.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

3 files changed, 143 insertions, 0 deletions

diff --git a/plat/freescale/imx8mq/include/fsl_sip.h b/plat/freescale/imx8mq/include/fsl_sip.h
new file mode 100644
index 00000000..73fa08d4
--- /dev/null
+++ b/plat/freescale/imx8mq/include/fsl_sip.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_FSL_SIP_H
+#define __SOC_FSL_SIP_H
+
+#define FSL_SIP_GPC			0xC2000000
+#define FSL_SIP_CONFIG_GPC_MASK		0x00
+#define FSL_SIP_CONFIG_GPC_UNMASK	0x01
+#define FSL_SIP_CONFIG_GPC_SET_WAKE	0x02
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x03
+
+#endif
diff --git a/plat/freescale/imx8mq/include/platform_def.h b/plat/freescale/imx8mq/include/platform_def.h
new file mode 100644
index 00000000..8d5dffb7
--- /dev/null
+++ b/plat/freescale/imx8mq/include/platform_def.h
@@ -0,0 +1,52 @@
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
+#define PLATFORM_STACK_SIZE		0X400
+#define CACHE_WRITEBACK_GRANULE		64
+
+#define PLAT_PRIMARY_CPU		0x0
+#define PLATFORM_MAX_CPU_PER_CLUSTER	4
+#define PLATFORM_CLUSTER_COUNT		1
+#define PLATFORM_CLUSTER0_CORE_COUNT	4
+#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER0_CORE_COUNT)
+
+#define IMX_PWR_LVL0		MPIDR_AFFLVL0
+#define IMX_PWR_LVL1		MPIDR_AFFLVL1
+#define IMX_PWR_LVL2		MPIDR_AFFLVL2
+
+#define PWR_DOMAIN_AT_MAX_LVL		1
+#define PLAT_MAX_PWR_LVL		2
+#define PLAT_MAX_OFF_STATE		2
+#define PLAT_MAX_RET_STATE		1
+
+#define BL31_BASE			0x40001000
+#define BL31_LIMIT			0x40021000
+
+/* non-secure uboot base */
+#define PLAT_NS_IMAGE_OFFSET		0x40021000
+
+/* GICv3 base address */
+#define PLAT_GICD_BASE			0x38800000
+#define PLAT_GICR_BASE			0x38880000
+
+#define PLAT_FSL_ADDR_SPACE_SIZE	(1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE	(1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE	(1ull << 32)
+
+#define MAX_XLAT_TABLES			4
+#define MAX_MMAP_REGIONS		16
+
+#define IMX_BOOT_UART_BASE		0x30860000
+#define IMX_BOOT_UART_CLK_IN_HZ		25000000 /* Select 25Mhz oscillator */
+#define PLAT_CRASH_UART_BASE		IMX_BOOT_UART_BASE
+#define PLAT__CRASH_UART_CLK_IN_HZ	25000000
+#define IMX_CONSOLE_BAUDRATE		115200
+
+#define IMX_ANAMIX_BASE	0x30360000
+#define IMX_SRC_BASE	0x30390000
+#define IMX_GPC_BASE	0x303a0000
+
+#define COUNTER_FREQUENCY		8000000 /* 8MHz */
+
+#define DEBUG_CONSOLE			0
+#define PLAT_IMX8M			1
diff --git a/plat/freescale/imx8mq/include/soc.h b/plat/freescale/imx8mq/include/soc.h
new file mode 100644
index 00000000..ebce7ea8
--- /dev/null
+++ b/plat/freescale/imx8mq/include/soc.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __IMX_SOC_H
+#define __IMX_SOC_H
+
+enum imx_cpu_pwr_mode {
+	WAIT_CLOCKED,			/* wfi only */
+	WAIT_UNCLOCKED,			/* WAIT */
+	WAIT_UNCLOCKED_POWER_OFF,	/* WAIT + SRPG */
+	STOP_POWER_ON,			/* just STOP */
+	STOP_POWER_OFF,			/* STOP + SRPG */
+};
+
+enum imx_gpc_slot {
+	A53_CORE0,
+	A53_CORE1,
+	A53_CORE2,
+	A53_CORE3,
+	A53_SCU,
+};
+
+enum imx_gpc_pu_slot {
+	FAST_MEGA_MIX,
+	MIPI_PHY,
+	PCIE1_PHY,
+	OTG1_PHY,
+	OTG2_PHY,
+	RESERVED,
+	CORE1_M4,
+	DDR1_PHY,
+	DDR2_PHY,
+	GPU,
+	VPU,
+	HDMI_PHY,
+	DSIP,
+	MIPI_CSI1,
+	MIPI_CSI2,
+	PCIE2_PHY,
+};
+
+void imx_gpc_set_m_core_pgc(unsigned int cpu, bool pdn);
+void imx_gpc_set_lpm_mode(enum imx_cpu_pwr_mode mode);
+void imx_gpc_set_cpu_power_gate_by_lpm(unsigned int cpu, bool pdn);
+void imx_gpc_set_plat_power_gate_by_lpm(bool pdn);
+void imx_gpc_set_core_pdn_pup_by_software(unsigned int cpu, bool pdn);
+void imx_gpc_set_cpu_ppower_gate_by_wfi(unsigned int cpu, bool pdn);
+void imx_gpc_pre_suspend(bool arm_power_off);
+void imx_gpc_post_resume(void);
+void imx_gpc_init(void);
+
+
+void imx_enable_cpu(unsigned int cpu, bool enable);
+int imx_is_m4_enabled(void);
+void imx_set_cpu_jump_addr(unsigned int cpu, void *jump_addr);
+#endif /* __IMX_SOC_H */