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authorAnson Huang <Anson.Huang@nxp.com>2017-08-16 22:09:45 +0800
committerAnson Huang <Anson.Huang@nxp.com>2017-08-17 00:53:57 +0800
commit685dddb758f14790299f78844146d9b12a731bac (patch)
tree785a7fb7978a8caf3cbe1ff3477f4e2a0c41dd64 /plat/freescale/imx8mq/imx8m_bl31_setup.c
parentf8180a6cb378839df965a7e0c71291caa886281e (diff)
imx8mq: enable PU power domain
- USB PHY reset bit in SRC needs to be clear before doing USB PHY power gating in GPC, only needs to do once; - Need to handle GPC_PU_PWRHSK during power up/down; - Enable GPC pu power gate support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/freescale/imx8mq/imx8m_bl31_setup.c')
-rw-r--r--plat/freescale/imx8mq/imx8m_bl31_setup.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/plat/freescale/imx8mq/imx8m_bl31_setup.c b/plat/freescale/imx8mq/imx8m_bl31_setup.c
index 21b7fdf9..132deb37 100644
--- a/plat/freescale/imx8mq/imx8m_bl31_setup.c
+++ b/plat/freescale/imx8mq/imx8m_bl31_setup.c
@@ -177,10 +177,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
mmio_write_32(0x32df004c, 0x0);
mmio_write_32(0x32df0050, 0x0);
- mmio_write_32(0x303a00ec, 0x0000ffff);
- /* Power up VPU, DISP, GPU etc */
- mmio_write_32(0x303a00f8, 0x3fef);
-
#if DEBUG_CONSOLE
console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
IMX_CONSOLE_BAUDRATE);