diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2017-07-22 00:51:49 +0800 |
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committer | Anson Huang <Anson.Huang@nxp.com> | 2017-07-26 00:26:25 +0800 |
commit | 4bc0aa353b8e0468d8e088e9d78cff2401803aa3 (patch) | |
tree | 07998c37614aa23935f40f2faa886e9a4d939695 /plat/freescale/imx8mq/gpc.c | |
parent | 72b305dbaecf7286c73126f1c8777fac6224c9f0 (diff) |
imx8mq: do NOT enable all PU power during boot up
No need to enable all PU power during boot up, module driver
will enable their power domain as needed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/freescale/imx8mq/gpc.c')
-rw-r--r-- | plat/freescale/imx8mq/gpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index 7938200a..d0b3a053 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -483,8 +483,8 @@ void imx_gpc_init(void) val |= 1 << 31; mmio_write_32(IMX_GPC_BASE + GPC_LPCR_M4, val); - /* set mega/fast mix in A53 domain */ - mmio_write_32(IMX_GPC_BASE + GPC_PGC_CPU_0_1_MAPPING, 0x1); + /* set all mix/PU in A53 domain */ + mmio_write_32(IMX_GPC_BASE + GPC_PGC_CPU_0_1_MAPPING, 0xfffd); /* set SCU timming */ mmio_write_32(IMX_GPC_BASE + GPC_PGC_SCU_TIMMING, |