Add i.MX8 SoCs support

This patch adds i.MX8 SoCs ATFW support, including below
basic features:

* LPUART
* SCFW RPC
* SMP boot up

Each SoC will have its own platform definition and driver
to support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

8 files changed, 1208 insertions, 0 deletions

diff --git a/plat/freescale/common/sci/ipc.c b/plat/freescale/common/sci/ipc.c
new file mode 100755
index 00000000..e1650d25
--- /dev/null
+++ b/plat/freescale/common/sci/ipc.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sci/scfw.h>
+#include <sci/ipc.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+
+#include "mx8_mu.h"
+
+void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, bool no_resp)
+{
+	sc_ipc_write(ipc, msg);
+	if (!no_resp)
+		sc_ipc_read(ipc, msg);
+}
+
+sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id)
+{
+	uint32_t base = id;
+	uint32_t i;
+	
+	/* Get MU base associated with IPC channel */
+	if ((ipc == NULL) || (base == 0))
+		return SC_ERR_IPC;
+
+	/* Init MU */
+	MU_Init(base);
+
+	/* Enable all RX interrupts */
+	for (i = 0; i < MU_RR_COUNT; i++) {
+		MU_EnableRxFullInt(base, i);
+	}
+
+	/* Return MU address as handle */
+	*ipc = (sc_ipc_t) id;
+
+	return SC_ERR_NONE;
+}
+
+void sc_ipc_close(sc_ipc_t ipc)
+{
+	uint32_t base = ipc;
+
+	if (base != 0)
+		MU_Init(base);
+}
+
+void sc_ipc_read(sc_ipc_t ipc, void *data)
+{
+	uint32_t base = ipc;
+	sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data;
+	uint8_t count = 0;
+
+	/* Check parms */
+	if ((base == 0) || (msg == NULL))
+		return;
+
+	/* Read first word */
+	MU_ReceiveMsg(base, 0, (uint32_t*) msg);   
+	count++;
+
+	/* Check size */
+	if (msg->size > SC_RPC_MAX_MSG) {
+		*((uint32_t*) msg) = 0;
+		return;
+	}
+	
+	/* Read remaining words */
+	while (count < msg->size) {
+		MU_ReceiveMsg(base, count % MU_RR_COUNT,
+			&(msg->DATA.d32[count - 1]));   
+		count++;
+	}
+}
+
+void sc_ipc_write(sc_ipc_t ipc, void *data)
+{
+	sc_rpc_msg_t *msg = (sc_rpc_msg_t*) data;
+	uint32_t base = ipc;
+	uint8_t count = 0;
+
+	/* Check parms */
+	if ((base == 0) || (msg == NULL))
+		return;
+
+	/* Check size */
+	if (msg->size > SC_RPC_MAX_MSG)
+		return;
+
+	/* Write first word */
+	MU_SendMessage(base, 0, *((uint32_t*) msg));   
+	count++;
+	
+	/* Write remaining words */
+	while (count < msg->size) {
+		MU_SendMessage(base, count % MU_TR_COUNT,
+			msg->DATA.d32[count - 1]);   
+		count++;
+	}
+}
+
diff --git a/plat/freescale/common/sci/mx8_mu.c b/plat/freescale/common/sci/mx8_mu.c
new file mode 100644
index 00000000..e983caef
--- /dev/null
+++ b/plat/freescale/common/sci/mx8_mu.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <mmio.h>
+#include "mx8_mu.h"
+
+void MU_EnableRxFullInt(uint32_t base, uint32_t index)
+{
+	uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
+
+	reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
+	reg |= MU_CR_RIE0_MASK1 >> index;
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
+
+void MU_EnableGeneralInt(uint32_t base, uint32_t index)
+{
+	uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1);
+
+	reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
+	reg |= MU_CR_GIE0_MASK1 >> index;
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
+
+void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg)
+{
+	uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
+
+	/* Wait TX register to be empty. */
+	while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
+		;
+	mmio_write_32(base + MU_ATR0_OFFSET1 + (regIndex * 4), msg);
+}
+
+void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg)
+{
+	uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
+
+	/* Wait RX register to be full. */
+	while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask))
+		;
+	*msg = mmio_read_32(base + MU_ARR0_OFFSET1 + (regIndex * 4));
+}
+
+void MU_Init(uint32_t base)
+{
+	uint32_t reg;
+
+	reg = mmio_read_32(base + MU_ACR_OFFSET1);
+	/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
+	reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
+			| MU_CR_GIRn_MASK1 | MU_CR_Fn_MASK1);
+	mmio_write_32(base + MU_ACR_OFFSET1, reg);
+}
diff --git a/plat/freescale/common/sci/mx8_mu.h b/plat/freescale/common/sci/mx8_mu.h
new file mode 100644
index 00000000..c0d9f76d
--- /dev/null
+++ b/plat/freescale/common/sci/mx8_mu.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <types.h>
+
+#define MU_ATR0_OFFSET1		0x0
+#define MU_ARR0_OFFSET1		0x10
+#define MU_ASR_OFFSET1		0x20
+#define MU_ACR_OFFSET1		0x24
+#define MU_TR_COUNT1		4
+#define MU_RR_COUNT1		4
+
+#define MU_CR_GIEn_MASK1	(0xF << 28)
+#define MU_CR_RIEn_MASK1	(0xF << 24)
+#define MU_CR_TIEn_MASK1	(0xF << 20)
+#define MU_CR_GIRn_MASK1	(0xF << 16)
+#define MU_CR_NMI_MASK1		(1 << 3)
+#define MU_CR_Fn_MASK1		0x7
+
+#define MU_SR_TE0_MASK1		(1 << 23)
+#define MU_SR_RF0_MASK1		(1 << 27)
+#define MU_CR_RIE0_MASK1	(1 << 27)
+#define MU_CR_GIE0_MASK1	(1 << 31)
+
+#define MU_TR_COUNT			4
+#define MU_RR_COUNT			4
+
+void MU_Init(uint32_t base);
+void MU_SendMessage(uint32_t base, uint32_t regIndex, uint32_t msg);
+void MU_ReceiveMsg(uint32_t base, uint32_t regIndex, uint32_t *msg);
+void MU_EnableGeneralInt(uint32_t base, uint32_t index);
+void MU_EnableRxFullInt(uint32_t base, uint32_t index);
diff --git a/plat/freescale/common/sci/sci_api.mk b/plat/freescale/common/sci/sci_api.mk
new file mode 100755
index 00000000..4a103da8
--- /dev/null
+++ b/plat/freescale/common/sci/sci_api.mk
@@ -0,0 +1,33 @@
+#
+# Copyright 2017 NXP
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of NXP nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+
+BL31_SOURCES		+=	plat/freescale/common/sci/ipc.c				\
+				plat/freescale/common/sci/mx8_mu.c			\
+				plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c	\
+				plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
diff --git a/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c b/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c
new file mode 100644
index 00000000..3bc7740b
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pad/pad_rpc_clnt.c
@@ -0,0 +1,418 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * File containing client-side RPC functions for the PAD service. These
+ * function are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+#include <sci/svc/pad/api.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pad_set_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t mux, sc_pad_config_t config, sc_pad_iso_t iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_MUX;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = mux;
+    RPC_D8(&msg, 3) = config;
+    RPC_D8(&msg, 4) = iso;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP;
+    RPC_D32(&msg, 0) = ctrl;
+    RPC_D16(&msg, 4) = pin;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t dse, bool sre, bool hys, bool pe,
+    sc_pad_28lpp_ps_t ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28LPP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = dse;
+    RPC_D8(&msg, 3) = ps;
+    RPC_D8(&msg, 4) = sre;
+    RPC_D8(&msg, 5) = hys;
+    RPC_D8(&msg, 6) = pe;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_WAKEUP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = wakeup;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t mux,
+    sc_pad_config_t config, sc_pad_iso_t iso, uint32_t ctrl,
+    sc_pad_wakeup_t wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_ALL;
+    RPC_D32(&msg, 0) = ctrl;
+    RPC_D16(&msg, 4) = pin;
+    RPC_D8(&msg, 6) = mux;
+    RPC_D8(&msg, 7) = config;
+    RPC_D8(&msg, 8) = iso;
+    RPC_D8(&msg, 9) = wakeup;
+    RPC_SIZE(&msg) = 4;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_mux(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *mux, sc_pad_config_t *config, sc_pad_iso_t *iso)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_MUX;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+        *mux = RPC_D8(&msg, 0);
+    if (config != NULL)
+        *config = RPC_D8(&msg, 1);
+    if (iso != NULL)
+        *iso = RPC_D8(&msg, 2);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp(sc_ipc_t ipc, sc_pin_t pin, uint32_t *ctrl)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (ctrl != NULL)
+        *ctrl = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28lpp(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28lpp_dse_t *dse, bool *sre, bool *hys, bool *pe,
+    sc_pad_28lpp_ps_t *ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28LPP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+        *dse = RPC_D8(&msg, 0);
+    if (ps != NULL)
+        *ps = RPC_D8(&msg, 1);
+    if (sre != NULL)
+        *sre = RPC_D8(&msg, 2);
+    if (hys != NULL)
+        *hys = RPC_D8(&msg, 3);
+    if (pe != NULL)
+        *pe = RPC_D8(&msg, 4);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_wakeup(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_WAKEUP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (wakeup != NULL)
+        *wakeup = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_all(sc_ipc_t ipc, sc_pin_t pin, uint8_t *mux,
+    sc_pad_config_t *config, sc_pad_iso_t *iso, uint32_t *ctrl,
+    sc_pad_wakeup_t *wakeup)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_ALL;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (ctrl != NULL)
+        *ctrl = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    if (mux != NULL)
+        *mux = RPC_D8(&msg, 4);
+    if (config != NULL)
+        *config = RPC_D8(&msg, 5);
+    if (iso != NULL)
+        *iso = RPC_D8(&msg, 6);
+    if (wakeup != NULL)
+        *wakeup = RPC_D8(&msg, 7);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t dse, sc_pad_28fdsoi_ps_t ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = dse;
+    RPC_D8(&msg, 3) = ps;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi(sc_ipc_t ipc, sc_pin_t pin,
+    sc_pad_28fdsoi_dse_t *dse, sc_pad_28fdsoi_ps_t *ps)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (dse != NULL)
+        *dse = RPC_D8(&msg, 0);
+    if (ps != NULL)
+        *ps = RPC_D8(&msg, 1);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t compen, bool fastfrz, uint8_t rasrcp, uint8_t rasrcn,
+    bool nasrc_sel)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET_GP_28FDSOI_COMP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_D8(&msg, 2) = compen;
+    RPC_D8(&msg, 3) = rasrcp;
+    RPC_D8(&msg, 4) = rasrcn;
+    RPC_D8(&msg, 5) = fastfrz;
+    RPC_D8(&msg, 6) = nasrc_sel;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get_gp_28fdsoi_comp(sc_ipc_t ipc, sc_pin_t pin,
+    uint8_t *compen, bool *fastfrz, uint8_t *rasrcp, uint8_t *rasrcn,
+    bool *nasrc_sel, bool *compok, uint8_t *nasrc)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET_GP_28FDSOI_COMP;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (compen != NULL)
+        *compen = RPC_D8(&msg, 0);
+    if (rasrcp != NULL)
+        *rasrcp = RPC_D8(&msg, 1);
+    if (rasrcn != NULL)
+        *rasrcn = RPC_D8(&msg, 2);
+    if (nasrc != NULL)
+        *nasrc = RPC_D8(&msg, 3);
+    if (fastfrz != NULL)
+        *fastfrz = RPC_D8(&msg, 4);
+    if (nasrc_sel != NULL)
+        *nasrc_sel = RPC_D8(&msg, 5);
+    if (compok != NULL)
+        *compok = RPC_D8(&msg, 6);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_set(sc_ipc_t ipc, sc_pin_t pin, uint32_t val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_SET;
+    RPC_D32(&msg, 0) = val;
+    RPC_D16(&msg, 4) = pin;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pad_get(sc_ipc_t ipc, sc_pin_t pin, uint32_t *val)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PAD;
+    RPC_FUNC(&msg) = PAD_FUNC_GET;
+    RPC_D16(&msg, 0) = pin;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (val != NULL)
+        *val = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pad/rpc.h b/plat/freescale/common/sci/svc/pad/rpc.h
new file mode 100644
index 00000000..25f2ce7e
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pad/rpc.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the PAD RPC implementation.
+ *
+ * @addtogroup PAD_SVC
+ * @{
+ */
+
+#ifndef _SC_PAD_RPC_H
+#define _SC_PAD_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/* Types */
+
+/*!
+ * This type is used to indicate RPC PAD function calls.
+ */
+typedef enum pad_func_e
+{
+    PAD_FUNC_UNKNOWN, //!< Unknown function
+    PAD_FUNC_SET_MUX, //!< Index for pad_set_mux() RPC call
+    PAD_FUNC_SET_GP, //!< Index for pad_set_gp() RPC call
+    PAD_FUNC_SET_GP_28LPP, //!< Index for pad_set_gp_28lpp() RPC call
+    PAD_FUNC_SET_WAKEUP, //!< Index for pad_set_wakeup() RPC call
+    PAD_FUNC_SET_ALL, //!< Index for pad_set_all() RPC call
+    PAD_FUNC_GET_MUX, //!< Index for pad_get_mux() RPC call
+    PAD_FUNC_GET_GP, //!< Index for pad_get_gp() RPC call
+    PAD_FUNC_GET_GP_28LPP, //!< Index for pad_get_gp_28lpp() RPC call
+    PAD_FUNC_GET_WAKEUP, //!< Index for pad_get_wakeup() RPC call
+    PAD_FUNC_GET_ALL, //!< Index for pad_get_all() RPC call
+    PAD_FUNC_SET_GP_28FDSOI, //!< Index for pad_set_gp_28fdsoi() RPC call
+    PAD_FUNC_GET_GP_28FDSOI, //!< Index for pad_get_gp_28fdsoi() RPC call
+    PAD_FUNC_SET_GP_28FDSOI_COMP, //!< Index for pad_set_gp_28fdsoi_comp() RPC call
+    PAD_FUNC_GET_GP_28FDSOI_COMP, //!< Index for pad_get_gp_28fdsoi_comp() RPC call
+    PAD_FUNC_SET, //!< Index for pad_set() RPC call
+    PAD_FUNC_GET, //!< Index for pad_get() RPC call
+} pad_func_t;
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PAD RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PAD RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pad_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* _SC_PAD_RPC_H */
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c b/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
new file mode 100755
index 00000000..fc91fad1
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pm/pm_rpc_clnt.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * File containing client-side RPC functions for the PM service. These
+ * function are ported to clients that communicate to the SC.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+/* Includes */
+
+#include <sci/types.h>
+#include <sci/svc/rm/api.h>
+#include <sci/svc/pm/api.h>
+#include <sci/rpc.h>
+#include <stdlib.h>
+#include "rpc.h"
+
+/* Local Defines */
+
+/* Local Types */
+
+/* Local Functions */
+
+sc_err_t sc_pm_set_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_SYS_POWER_MODE;
+    RPC_D8(&msg, 0) = pt;
+    RPC_D8(&msg, 1) = mode;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_SYS_POWER_MODE;
+    RPC_D8(&msg, 0) = pt;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+        *mode = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_RESOURCE_POWER_MODE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = mode;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_power_mode_t *mode)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_RESOURCE_POWER_MODE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    if (mode != NULL)
+        *mode = RPC_D8(&msg, 0);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_SET_CLOCK_RATE;
+    RPC_D32(&msg, 0) = *rate;
+    RPC_D16(&msg, 4) = resource;
+    RPC_D8(&msg, 6) = clk;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    *rate = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, sc_pm_clock_rate_t *rate)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_GET_CLOCK_RATE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = clk;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    if (rate != NULL)
+        *rate = RPC_D32(&msg, 0);
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource,
+    sc_pm_clk_t clk, bool enable, bool autog)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_CLOCK_ENABLE;
+    RPC_D16(&msg, 0) = resource;
+    RPC_D8(&msg, 2) = clk;
+    RPC_D8(&msg, 3) = enable;
+    RPC_D8(&msg, 4) = autog;
+    RPC_SIZE(&msg) = 3;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_rsrc_t resource_cpu, sc_faddr_t boot_addr,
+    sc_rsrc_t resource_mu)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_BOOT;
+    RPC_D32(&msg, 0) = boot_addr >> 32;
+    RPC_D32(&msg, 4) = boot_addr;
+    RPC_D16(&msg, 8) = resource_cpu;
+    RPC_D16(&msg, 10) = resource_mu;
+    RPC_D8(&msg, 12) = pt;
+    RPC_SIZE(&msg) = 5;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_REBOOT;
+    RPC_D8(&msg, 0) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, true);
+
+    return;
+}
+
+void sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason)
+{
+    sc_rpc_msg_t msg;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_RESET_REASON;
+    RPC_SIZE(&msg) = 1;
+
+    sc_call_rpc(ipc, &msg, true);
+
+    if (reason != NULL)
+        *reason = RPC_D8(&msg, 0);
+    return;
+}
+
+sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable,
+    sc_faddr_t address)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_CPU_START;
+    RPC_D32(&msg, 0) = address >> 32;
+    RPC_D32(&msg, 4) = address;
+    RPC_D16(&msg, 8) = resource;
+    RPC_D8(&msg, 10) = enable;
+    RPC_SIZE(&msg) = 4;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reboot_partition(sc_ipc_t ipc, sc_rm_pt_t pt,
+    sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_REBOOT_PARTITION;
+    RPC_D8(&msg, 0) = pt;
+    RPC_D8(&msg, 1) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type)
+{
+    sc_rpc_msg_t msg;
+    uint8_t result;
+
+    RPC_VER(&msg) = SC_RPC_VERSION;
+    RPC_SVC(&msg) = SC_RPC_SVC_PM;
+    RPC_FUNC(&msg) = PM_FUNC_RESET;
+    RPC_D8(&msg, 0) = type;
+    RPC_SIZE(&msg) = 2;
+
+    sc_call_rpc(ipc, &msg, false);
+
+    result = RPC_R8(&msg);
+    return (sc_err_t) result;
+}
+
+/**@}*/
+
diff --git a/plat/freescale/common/sci/svc/pm/rpc.h b/plat/freescale/common/sci/svc/pm/rpc.h
new file mode 100755
index 00000000..2ce1b5c9
--- /dev/null
+++ b/plat/freescale/common/sci/svc/pm/rpc.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of NXP nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*!
+ * Header file for the PM RPC implementation.
+ *
+ * @addtogroup PM_SVC
+ * @{
+ */
+
+#ifndef _SC_PM_RPC_H
+#define _SC_PM_RPC_H
+
+/* Includes */
+
+/* Defines */
+
+/* Types */
+
+/*!
+ * This type is used to indicate RPC PM function calls.
+ */
+typedef enum pm_func_e
+{
+    PM_FUNC_UNKNOWN, //!< Unknown function
+    PM_FUNC_SET_SYS_POWER_MODE, //!< Index for pm_set_sys_power_mode() RPC call
+    PM_FUNC_GET_SYS_POWER_MODE, //!< Index for pm_get_sys_power_mode() RPC call
+    PM_FUNC_SET_RESOURCE_POWER_MODE, //!< Index for pm_set_resource_power_mode() RPC call
+    PM_FUNC_GET_RESOURCE_POWER_MODE, //!< Index for pm_get_resource_power_mode() RPC call
+    PM_FUNC_SET_CLOCK_RATE, //!< Index for pm_set_clock_rate() RPC call
+    PM_FUNC_GET_CLOCK_RATE, //!< Index for pm_get_clock_rate() RPC call
+    PM_FUNC_CLOCK_ENABLE, //!< Index for pm_clock_enable() RPC call
+    PM_FUNC_BOOT, //!< Index for pm_boot() RPC call
+    PM_FUNC_REBOOT, //!< Index for pm_reboot() RPC call
+    PM_FUNC_RESET_REASON, //!< Index for pm_reset_reason() RPC call
+    PM_FUNC_CPU_START, //!< Index for pm_cpu_start() RPC call
+    PM_FUNC_REBOOT_PARTITION, //!< Index for pm_reboot_partition() RPC call
+    PM_FUNC_RESET, //!< Index for pm_reset() RPC call
+} pm_func_t;
+
+/* Functions */
+
+/*!
+ * This function dispatches an incoming PM RPC request.
+ *
+ * @param[in]     caller_pt   caller partition
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_dispatch(sc_rm_pt_t caller_pt, sc_rpc_msg_t *msg);
+
+/*!
+ * This function translates and dispatches an PM RPC request.
+ *
+ * @param[in]     ipc         IPC handle
+ * @param[in]     msg         pointer to RPC message
+ */
+void pm_xlate(sc_ipc_t ipc, sc_rpc_msg_t *msg);
+
+#endif /* _SC_PM_RPC_H */
+
+/**@}*/
+