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authorAnson Huang <Anson.Huang@nxp.com>2017-08-14 23:24:27 +0800
committerAnson Huang <Anson.Huang@nxp.com>2017-08-25 02:55:00 +0800
commit61d8cbdf027c0b00ca4c2dbe00d6e0b896cc7b42 (patch)
tree45da8f1a2744ae9b959bf93a9f9cacb5642e89a3 /plat/freescale/common/cpufreq.c
parent685dddb758f14790299f78844146d9b12a731bac (diff)
i.mx8qm/i.mx8qxp: add SIP cpu-freq support
Linux kernel will issue cpu-freq scale via SIP, ATF calls SCFW API to finish the CPU frequency scale. Move SIP service code from i.mx8mq to common place for all i.mx SoCs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'plat/freescale/common/cpufreq.c')
-rw-r--r--plat/freescale/common/cpufreq.c57
1 files changed, 57 insertions, 0 deletions
diff --git a/plat/freescale/common/cpufreq.c b/plat/freescale/common/cpufreq.c
new file mode 100644
index 00000000..75f005dd
--- /dev/null
+++ b/plat/freescale/common/cpufreq.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <smcc_helpers.h>
+#include <std_svc.h>
+#include <types.h>
+#include <platform_def.h>
+#include <fsl_sip.h>
+#include <sci/sci.h>
+
+extern sc_ipc_t ipc_handle;
+
+const static int ap_cluster_index[2] = {
+ SC_R_A53, SC_R_A72,
+};
+
+static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq)
+{
+ sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq;
+
+#ifdef PLAT_IMX8QM
+ sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate);
+#endif
+#ifdef PLAT_IMX8QXP
+ sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate);
+#endif
+}
+
+int imx_cpufreq_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3)
+{
+ switch(x1) {
+ case FSL_SIP_SET_CPUFREQ:
+ imx_cpufreq_set_target(x2, x3);
+ break;
+ default:
+ return SMC_UNK;
+ }
+
+ return 0;
+}