diff options
author | Julius Werner <jwerner@chromium.org> | 2019-07-09 14:02:43 -0700 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2019-08-01 13:45:03 -0700 |
commit | 402b3cf8766fe2cb4ae462f7ee7761d08a1ba56c (patch) | |
tree | bf3de0c17a38822188847b7bdaad7f70441637b0 /plat/arm | |
parent | d5dfdeb65ff5b7f24dded201d2945c7b74565ce8 (diff) |
Switch AARCH32/AARCH64 to __aarch64__
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__.
All common C compilers pre-define the same macros to signal which
architecture the code is being compiled for: __arm__ for AArch32 (or
earlier versions) and __aarch64__ for AArch64. There's no need for TF-A
to define its own custom macros for this. In order to unify code with
the export headers (which use __aarch64__ to avoid another dependency),
let's deprecate the AARCH32 and AARCH64 macros and switch the code base
over to the pre-defined standard macro. (Since it is somewhat
unintuitive that __arm__ only means AArch32, let's standardize on only
using __aarch64__.)
Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200
Signed-off-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'plat/arm')
-rw-r--r-- | plat/arm/board/fvp/fvp_common.c | 4 | ||||
-rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 4 | ||||
-rw-r--r-- | plat/arm/board/fvp_ve/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/juno/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/juno/juno_common.c | 4 | ||||
-rw-r--r-- | plat/arm/board/n1sdp/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/rde1edge/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/sgi575/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/board/sgm775/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/arm/common/arm_bl1_setup.c | 8 | ||||
-rw-r--r-- | plat/arm/common/arm_bl2_el3_setup.c | 6 | ||||
-rw-r--r-- | plat/arm/common/arm_bl2_setup.c | 8 | ||||
-rw-r--r-- | plat/arm/common/arm_bl2u_setup.c | 6 | ||||
-rw-r--r-- | plat/arm/common/arm_common.c | 4 | ||||
-rw-r--r-- | plat/arm/common/arm_gicv3.c | 4 | ||||
-rw-r--r-- | plat/arm/common/arm_nor_psci_mem_protect.c | 2 | ||||
-rw-r--r-- | plat/arm/common/arm_pm.c | 2 | ||||
-rw-r--r-- | plat/arm/common/execution_state_switch.c | 4 |
19 files changed, 35 insertions, 35 deletions
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index b885b47a..36cd5009 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -81,7 +81,7 @@ const mmap_region_t plat_arm_mmap[] = { MAP_DEVICE0, MAP_DEVICE1, ARM_MAP_NS_DRAM1, -#ifdef AARCH64 +#ifdef __aarch64__ ARM_MAP_DRAM2, #endif #ifdef SPD_tspd @@ -150,7 +150,7 @@ const mmap_region_t plat_arm_secure_partition_mmap[] = { #endif #ifdef IMAGE_BL32 const mmap_region_t plat_arm_mmap[] = { -#ifdef AARCH32 +#ifndef __aarch64__ ARM_MAP_SHARED_RAM, ARM_V2M_MAP_MEM_PROTECT, #endif diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 207cd31d..4f262770 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -120,7 +120,7 @@ #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) #endif -#ifdef AARCH32 +#ifndef __aarch64__ /* * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is * calculated using the current SP_MIN PROGBITS debug size plus the sizes of @@ -259,7 +259,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index b3b36726..4e575e1a 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -331,7 +331,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index d693c26a..83aeeb4b 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -291,7 +291,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifdef AARCH64 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c index 118c19ab..98c5d3c9 100644 --- a/plat/arm/board/juno/juno_common.c +++ b/plat/arm/board/juno/juno_common.c @@ -37,7 +37,7 @@ const mmap_region_t plat_arm_mmap[] = { CSS_MAP_DEVICE, SOC_CSS_MAP_DEVICE, ARM_MAP_NS_DRAM1, -#ifdef AARCH64 +#ifdef __aarch64__ ARM_MAP_DRAM2, #endif #ifdef SPD_tspd @@ -74,7 +74,7 @@ const mmap_region_t plat_arm_mmap[] = { #endif #ifdef IMAGE_BL32 const mmap_region_t plat_arm_mmap[] = { -#ifdef AARCH32 +#ifndef __aarch64__ ARM_MAP_SHARED_RAM, #ifdef PLAT_ARM_MEM_PROT_ADDR ARM_V2M_MAP_MEM_PROTECT, diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index ff583a90..7348bf5e 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -34,7 +34,7 @@ * space the physical & virtual address space limits are extended to * 40-bits. */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 40) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 40) #else diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h index c62cda85..50b04f04 100644 --- a/plat/arm/board/rde1edge/include/platform_def.h +++ b/plat/arm/board/rde1edge/include/platform_def.h @@ -29,7 +29,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index 2c7b8bda..580ab8e6 100644 --- a/plat/arm/board/rdn1edge/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -30,7 +30,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h index 883403bb..f00146f9 100644 --- a/plat/arm/board/sgi575/include/platform_def.h +++ b/plat/arm/board/sgi575/include/platform_def.h @@ -30,7 +30,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h index 3e1fdd12..27d1b330 100644 --- a/plat/arm/board/sgm775/include/platform_def.h +++ b/plat/arm/board/sgm775/include/platform_def.h @@ -15,7 +15,7 @@ /* * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes */ -#ifndef AARCH32 +#ifdef __aarch64__ #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) #else diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 8905bb05..b19a7c39 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -121,11 +121,11 @@ void arm_bl1_plat_arch_setup(void) }; setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el3(0); -#endif /* AARCH32 */ +#else + enable_mmu_svc_mon(0); +#endif /* __aarch64__ */ arm_setup_romlib(); } diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c index 0c01c872..97b5a888 100644 --- a/plat/arm/common/arm_bl2_el3_setup.c +++ b/plat/arm/common/arm_bl2_el3_setup.c @@ -83,10 +83,10 @@ void arm_bl2_el3_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el3(0); +#else + enable_mmu_svc_mon(0); #endif } diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 32617f68..cdf87ca5 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -128,10 +128,10 @@ void arm_bl2_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); #endif arm_setup_romlib(); @@ -153,7 +153,7 @@ int arm_bl2_handle_post_image_load(unsigned int image_id) assert(bl_mem_params); switch (image_id) { -#ifdef AARCH64 +#ifdef __aarch64__ case BL32_IMAGE_ID: #ifdef SPD_opteed pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c index 9f44b9e6..3614c7d2 100644 --- a/plat/arm/common/arm_bl2u_setup.c +++ b/plat/arm/common/arm_bl2u_setup.c @@ -83,10 +83,10 @@ void arm_bl2u_plat_arch_setup(void) setup_page_tables(bl_regions, plat_arm_get_mmap()); -#ifdef AARCH32 - enable_mmu_svc_mon(0); -#else +#ifdef __aarch64__ enable_mmu_el1(0); +#else + enable_mmu_svc_mon(0); #endif arm_setup_romlib(); } diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index f5ce4d24..bc0cf9a8 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -59,7 +59,7 @@ uint32_t arm_get_spsr_for_bl32_entry(void) /******************************************************************************* * Gets SPSR for BL33 entry ******************************************************************************/ -#ifndef AARCH32 +#ifdef __aarch64__ uint32_t arm_get_spsr_for_bl33_entry(void) { unsigned int mode; @@ -97,7 +97,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void) SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); return spsr; } -#endif /* AARCH32 */ +#endif /* __aarch64__ */ /******************************************************************************* * Configures access to the system counter timer module. diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c index 93bebf34..7f4957fa 100644 --- a/plat/arm/common/arm_gicv3.c +++ b/plat/arm/common/arm_gicv3.c @@ -83,8 +83,8 @@ void __init plat_arm_gic_driver_init(void) * can use GIC system registers to manage interrupts and does * not need GIC interface base addresses to be configured. */ -#if (defined(AARCH32) && defined(IMAGE_BL32)) || \ - (defined(IMAGE_BL31) && !defined(AARCH32)) +#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \ + (defined(__aarch64__) && defined(IMAGE_BL31)) gicv3_driver_init(&arm_gic_data); #endif } diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c index 3a700598..b9181eb4 100644 --- a/plat/arm/common/arm_nor_psci_mem_protect.c +++ b/plat/arm/common/arm_nor_psci_mem_protect.c @@ -26,7 +26,7 @@ static mem_region_t arm_ram_ranges[] = { {DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE}, -#ifdef AARCH64 +#ifdef __aarch64__ {ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT}, #endif }; diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c index cb87bafd..c95f4523 100644 --- a/plat/arm/common/arm_pm.c +++ b/plat/arm/common/arm_pm.c @@ -116,7 +116,7 @@ int arm_validate_ns_entrypoint(uintptr_t entrypoint) (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { return 0; } -#ifndef AARCH32 +#ifdef __aarch64__ if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { return 0; diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c index d4711302..00ac16ef 100644 --- a/plat/arm/common/execution_state_switch.c +++ b/plat/arm/common/execution_state_switch.c @@ -40,7 +40,7 @@ int arm_execution_state_switch(unsigned int smc_fid, void *handle) { /* Execution state can be switched only if EL3 is AArch64 */ -#ifdef AARCH64 +#ifdef __aarch64__ bool caller_64, thumb = false, from_el2; unsigned int el, endianness; u_register_t spsr, pc, scr, sctlr; @@ -173,7 +173,7 @@ invalid_param: SMC_RET1(handle, STATE_SW_E_PARAM); exec_denied: -#endif +#endif /* __aarch64__ */ /* State switch denied */ SMC_RET1(handle, STATE_SW_E_DENIED); } |