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| author | John Tsichritzis <john.tsichritzis@arm.com> | 2019-06-06 15:19:50 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-06-06 15:19:50 +0000 |
| commit | 74eaf2666df8cf33bf74f7c08b3d96ad2166c1d5 (patch) | |
| tree | 9be5f0dd901060c8ab9c032c36879c4085779e27 /plat/arm | |
| parent | 0f95565c40d54188dd072fe2b429046dbbd9a6a3 (diff) | |
| parent | 9c29e5f78e54cda2f323604332d167ae38d04d1a (diff) | |
Merge "FVP: Remove GIC initialisation from secondary core cold boot" into integration
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/fvp/aarch64/fvp_helpers.S | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/plat/arm/board/fvp/aarch64/fvp_helpers.S b/plat/arm/board/fvp/aarch64/fvp_helpers.S index 09f19f6c..8efc2386 100644 --- a/plat/arm/board/fvp/aarch64/fvp_helpers.S +++ b/plat/arm/board/fvp/aarch64/fvp_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,14 +16,6 @@ .globl plat_is_my_cpu_primary .globl plat_arm_calc_core_pos - .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res - mov_imm \x_tmp, V2M_SYSREGS_BASE + V2M_SYS_ID - ldr \w_tmp, [\x_tmp] - ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH - cmp \w_tmp, #BLD_GIC_VE_MMAP - csel \res, \param1, \param2, eq - .endm - /* ----------------------------------------------------- * void plat_secondary_cold_boot_setup (void); * @@ -50,35 +42,6 @@ func plat_secondary_cold_boot_setup str w0, [x1, #PPOFFR_OFF] /* --------------------------------------------- - * Disable GIC bypass as well - * --------------------------------------------- - */ - /* Check for GICv3 system register access */ - mrs x0, id_aa64pfr0_el1 - ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH - cmp x0, #1 - b.ne gicv2_bypass_disable - - /* Check for SRE enable */ - mrs x1, ICC_SRE_EL3 - tst x1, #ICC_SRE_SRE_BIT - b.eq gicv2_bypass_disable - - mrs x2, ICC_SRE_EL3 - orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT) - msr ICC_SRE_EL3, x2 - b secondary_cold_boot_wait - -gicv2_bypass_disable: - mov_imm x0, VE_GICC_BASE - mov_imm x1, BASE_GICC_BASE - fvp_choose_gicmmap x0, x1, x2, w2, x1 - mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) - orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) - str w0, [x1, #GICC_CTLR] - -secondary_cold_boot_wait: - /* --------------------------------------------- * There is no sane reason to come out of this * wfi so panic if we do. This cpu will be pow- * ered on and reset by the cpu_on pm api |