diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2019-07-23 15:18:58 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-07-23 15:18:58 +0000 |
| commit | 6ef6157e76b6cd95eb159d091898177e3bf886af (patch) | |
| tree | e7be80d174f4bb2f86d61a8c0b4c1d31a175ef81 /plat/arm | |
| parent | 4dc74ca387b047a085052b7b9ff4f9c81ce6dcd5 (diff) | |
| parent | 7428bbf4437e046b1bd5f43506abed2fb621b7bc (diff) | |
Merge "n1sdp: fix DMC ECC enablement sequence in N1SDP platform" into integration
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/n1sdp/n1sdp_bl31_setup.c | 9 | ||||
| -rw-r--r-- | plat/arm/board/n1sdp/n1sdp_def.h | 8 |
2 files changed, 17 insertions, 0 deletions
diff --git a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c index a831b89f..632af7b4 100644 --- a/plat/arm/board/n1sdp/n1sdp_bl31_setup.c +++ b/plat/arm/board/n1sdp/n1sdp_bl31_setup.c @@ -80,8 +80,17 @@ void dmc_ecc_setup(uint32_t ddr_size_gb) flush_dcache_range(ARM_DRAM2_BASE, dram2_size); INFO("Enabling ECC on DMCs\n"); + /* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ + mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); + mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_CONFIG); + + /* Enable ECC in DMCs */ mmio_setbits_32(N1SDP_DMC0_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); mmio_setbits_32(N1SDP_DMC1_ERR0CTLR0_REG, N1SDP_DMC_ERR0CTLR0_ECC_EN); + + /* Set DMCs to READY state */ + mmio_write_32(N1SDP_DMC0_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); + mmio_write_32(N1SDP_DMC1_MEMC_CMD_REG, N1SDP_DMC_MEMC_CMD_READY); } void copy_bl33(uint32_t src, uint32_t dst, uint32_t size) diff --git a/plat/arm/board/n1sdp/n1sdp_def.h b/plat/arm/board/n1sdp/n1sdp_def.h index b7f7213d..d43c5a47 100644 --- a/plat/arm/board/n1sdp/n1sdp_def.h +++ b/plat/arm/board/n1sdp/n1sdp_def.h @@ -25,10 +25,18 @@ #define N1SDP_SDS_BL33_INFO_OFFSET 0 #define N1SDP_SDS_BL33_INFO_SIZE 12 +/* DMC memory command registers */ +#define N1SDP_DMC0_MEMC_CMD_REG 0x4E000008 +#define N1SDP_DMC1_MEMC_CMD_REG 0x4E100008 + /* DMC ERR0CTLR0 registers */ #define N1SDP_DMC0_ERR0CTLR0_REG 0x4E000708 #define N1SDP_DMC1_ERR0CTLR0_REG 0x4E100708 +/* DMC memory commands */ +#define N1SDP_DMC_MEMC_CMD_CONFIG 0 +#define N1SDP_DMC_MEMC_CMD_READY 3 + /* DMC ECC enable bit in ERR0CTLR0 register */ #define N1SDP_DMC_ERR0CTLR0_ECC_EN 0x1 |