diff options
| author | Soby Mathew <soby.mathew@arm.com> | 2019-05-16 08:33:56 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-05-16 08:33:56 +0000 |
| commit | 482fc9c88840c7d9c74e1fa57a8e25a291cc02be (patch) | |
| tree | 1baf224d58fe4d1c4ab0f5b8d46f83bc53ccaca4 /plat/arm | |
| parent | d8b11091b6f9032c16fdc54218ceda10d21e3355 (diff) | |
| parent | 603b372e5349ef4bfc2fbea395787d64620a73d3 (diff) | |
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
* changes:
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
N1SDP: Fix DRAM2 start address
Add option for defining platform DRAM2 base
Disable speculative loads only if SSBS is supported
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 1 | ||||
| -rw-r--r-- | plat/arm/board/fvp_ve/include/platform_def.h | 3 | ||||
| -rw-r--r-- | plat/arm/board/n1sdp/include/platform_def.h | 3 | ||||
| -rw-r--r-- | plat/arm/common/arm_common.c | 10 |
4 files changed, 10 insertions, 7 deletions
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 6856a286..2313ab0c 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -48,6 +48,7 @@ /* No SCP in FVP */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x0) +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE UL(0x80000000) /* diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h index 1870442f..1b21c79d 100644 --- a/plat/arm/board/fvp_ve/include/platform_def.h +++ b/plat/arm/board/fvp_ve/include/platform_def.h @@ -25,7 +25,7 @@ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ ARM_DRAM1_SIZE - 1) -#define ARM_DRAM2_BASE UL(0x880000000) +#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ ARM_DRAM2_SIZE - 1) @@ -230,6 +230,7 @@ #define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ +#define PLAT_ARM_DRAM2_BASE ULL(0x880000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x80000000) /* diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h index adb957e5..0964f568 100644 --- a/plat/arm/board/n1sdp/include/platform_def.h +++ b/plat/arm/board/n1sdp/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -24,6 +24,7 @@ #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ +#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) #define PLAT_ARM_DRAM2_SIZE ULL(0x780000000) #if CSS_USE_SCMI_SDS_DRIVER diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 0442945b..f5ce4d24 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -127,12 +127,12 @@ void arm_configure_sys_timer(void) */ mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val); -#ifdef PLAT_juno +#if defined(PLAT_juno) || defined(PLAT_n1sdp) /* * Initialize CNTFRQ register in Non-secure CNTBase frame. - * This is only required for Juno, because it doesn't follow ARM ARM - * in that the value updated in CNTFRQ is not reflected in - * CNTBASEN_CNTFRQ. Hence update the value manually. + * This is only required for Juno and N1SDP, because they do not + * follow ARM ARM in that the value updated in CNTFRQ is not + * reflected in CNTBASEN_CNTFRQ. Hence update the value manually. */ mmio_write_32(ARM_SYS_CNT_BASE_NS + CNTBASEN_CNTFRQ, freq_val); #endif |